PDF HYM71V16655HCT6 Data sheet ( Hoja de datos )

Número de pieza	HYM71V16655HCT6
Descripción	PC100 SDRAM Unbuffered DIMM
Fabricantes	Hynix Semiconductor
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No Preview Available ! www.DataSheet4U.com 16Mx64 bits PC100 SDRAM Unbuffered DIMM based on 8Mx16 SDRAM with LVTTL, 4 banks & 4K Refresh HYM71V16655HCT6 Series DESCRIPTION The Hynix HYM71V16655HCT6 Series are 16Mx64bits Synchronous DRAM Modules. The modules are composed of eight 8Mx16bits CMOS Synchronous DRAMs in 400mil 54pin TSOP-II package, one 2Kbit EEPROM in 8pin TSSOP package on a 168pin glass-epoxy printed circuit board. Two 0.33uF and one 0.1uF decoupling capacitors per each SDRAM are mounted on the PCB. The Hynix HYM71V16655HCT6 Series are Dual In-line Memory Modules suitable for easy interchange and addition of 128Mbytes memory. The Hynix HYM71V16655HCT6 Series are fully synchronous operation referenced to the positive edge of the clock . All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. FEATURES • PC100MHz support • SDRAM internal banks : four banks • 168pin SDRAM Unbuffered DIMM • Module bank : two physical bank • Serial Presence Detect with EEPROM • Auto refresh and self refresh • 1.25” (31.75mm) Height PCB with double sided com- • 4096 refresh cycles / 64ms ponents • Programmable Burst Length and Burst Type • Single 3.3±0.3V power supply - 1, 2, 4 or 8 or Full page for Sequential Burst • All device pins are compatible with LVTTL interface - 1, 2, 4 or 8 for Interleave Burst • Data mask function by DQM • Programmable CAS Latency ; 2, 3 Clocks ORDERING INFORMATION Part No. HYM71V16M655HCT6-8 HYM71V16M655HCT6-P HYM71V16M655HCT6-S HYM71V16M655HCLT6-8 HYM71V16M655HCLT6-P HYM71V16M655HCLT6-S Clock Frequency 125MHz 100MHz 100MHz 125MHz 100MHz 100MHz Internal Bank 4 Banks Ref. 4K Power SDRAM Package Plating Normal Low Power TSOP-II Gold This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.5 / Mar. 2003 2 1 page www.DataSheet4U.com SERIAL PRESENCE DETECT PC100 SDRAM Unbuffered DIMM HYM71V16655HCT6 Series BYTE NUMBER BYTE0 BYTE1 BYTE2 BYTE3 BYTE4 BYTE5 BYTE6 BYTE7 BYTE8 BYTE9 BYTE10 BYTE11 BYTE12 BYTE13 BYTE14 BYTE15 BYTE16 BYTE17 BYTE18 BYTE19 BYTE20 BYTE21 BYTE22 BYTE23 BYTE24 BYTE25 BYTE26 BYTE27 BYTE28 BYTE29 BYTE30 BYTE31 BYTE32 BYTE33 BYTE34 BYTE35 BYTE36 ~61 BYTE62 BYTE63 BYTE64 BYTE65 ~71 BYTE72 FUNCTION DESCRIPTION # of Bytes Written into Serial Memory at Module Manufacturer Total # of Bytes of SPD Memory Device Fundamental Memory Type # of Row Addresses on This Assembly # of Column Addresses on This Assembly # of Module Banks on This Assembly Data Width of This Assembly Data Width of This Assembly (Continued) Voltage Interface Standard of This Assembly SDRAM Cycle Time @/CAS Latency=3 Access Time from Clock @/CAS Latency=3 DIMM Configuration Type Refresh Rate/Type Primary SDRAM Width Error Checking SDRAM Width Minimum Clock Delay Back to Back Random Column Address Burst Lenth Supported # of Banks on Each SDRAM Device SDRAM Device Attributes, /CAS Lataency SDRAM Device Attributes, /CS Lataency SDRAM Device Attributes, /WE Lataency SDRAM Module Attributes SDRAM Device Attributes, General SDRAM Cycle Time @/CAS Latency=2 Access Time from Clock @/CAS Latency=2 SDRAM Cycle Time @/CAS Latency=1 Access Time from Clock @/CAS Latency=1 Minimum Row Precharge Time (tRP) Minimum Row Active to Row Active Delay (tRRD) Minimum /RAS to /CAS Delay (tRCD) Minimum /RAS Pulse Width (tRAS) Module Bank Density Command and Address Signal Input Setup Time Command and Address Signal Input Hold Time Data Signal Input Setup Time Data Signal Input Hold Time Superset Information (may be used in future) SPD Revision Checksum for Byte 0~62 Manufacturer JEDEC ID Code ....Manufacturer JEDEC ID Code Manufacturing Location FUNCTION -8 -P -S 128 Bytes 256 Bytes SDRAM 12 9 2 Bank 64 Bits - LVTTL 8ns 10ns 10ns 6ns 6ns 6ns None 15.625us / Self Refresh Supported x16 None tCCD = 1 CLK 1,2,4,8,Full Page 4 Banks /CAS Latency=2,3 /CS Latency=0 /WE Latency=0 Neither Buffered nor Registered +/- 10% voltage tolerence, Burst Read Single Bit Write, Precharge All, Auto Precharge, Early RAS Precharge 8ns 10ns 12ns 6ns 6ns 6ns --- --- 20ns 20ns 20ns 16ns 20ns 20ns 20ns 20ns 20ns 48ns 50ns 50ns 64MB 2ns 2ns 2ns 1ns 1ns 1ns 2ns 2ns 2ns 1ns 1ns 1ns - Intel SPD 1.2B - Hynix JEDED ID Unused HSI (Korea Area) HSA (United States Area) HSE (Europe Area) HSJ (Japan Area) HSS(Singapore) Asia Area -8 80h 60h A0h 60h 00h 00h 14h 10h 14h 30h 20h 10h 20h 10h E8h VALUE -P 80h 08h 04h 0Ch 09h 02h 40h 00h 01h A0h 60h 00h 80h 10h 00h 01h 8Fh 04h 06h 01h 01h 00h 0Eh A0h 60h 00h 00h 14h 14h 14h 32h 10h 20h 10h 20h 10h 00h 12h 0Eh ADh FFh 0h 1h 2h 3h 4h 5h -S A0h 60h C0h 60h 00h 00h 14h 14h 14h 32h 20h 10h 20h 10h 2Eh NOTE 1 2 3, 8 10 Rev. 0.5 / Mar. 2003 6 5 Page www.DataSheet4U.com AC CHARACTERISTICS II PC100 SDRAM Unbuffered DIMM HYM71V16655HCT6 Series Parameter Symbol -8 Min Max -P Min Max -S Min Max Unit Note Operation tRC 68 - 70 - 70 - ns RAS Cycle Time Auto Refresh tRRC 68 - 70 - 70 - ns RAS to CAS Delay tRCD 20 - 20 - 20 - ns RAS Active Time tRAS 48 100K 50 100K 50 100K ns RAS Precharge Time tRP 20 - 20 - 20 - ns RAS to RAS Bank Active Delay tRRD 16 - 20 - 20 - ns CAS to CAS Delay tCCD 1 - 1 - 1 - CLK Write Command to Data-In Delay tWTL 0 - 0 - 0 - CLK Data-In to Precharge Command tDPL 1 - 1 - 1 - CLK Data-In to Active Command tDAL 4 - 3 - 3 - CLK DQM to Data-Out Hi-Z tDQZ 2 - 2 - 2 - CLK DQM to Data-In Mask tDQM 0 - 0 - 0 - CLK MRS to New Command tMRD 2 - 2 - 2 - CLK Precharge to Data CAS Latency = 3 tPROZ3 3 - 3 - 3 - CLK Output Hi-Z CAS Latency = 2 tPROZ2 2 - 2 - 2 - CLK Power Down Exit Time tPDE 1 - 1 - 1 - CLK Self Refresh Exit Time tSRE 1 - 1 - 1 - CLK 1 Refresh Time tREF - 64 - 64 - 64 ms Note : 1. A new command can be given tRRC after self refresh exit Rev. 0.5 / Mar. 2003 12 11 Page

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Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
HYM71V16655HCT6	PC100 SDRAM Unbuffered DIMM	Hynix Semiconductor
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