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Hynix Semiconductor - PC133 SDRAM Unbuffered DIMM

Numéro de référence HYM71V16635HCT6
Description PC133 SDRAM Unbuffered DIMM
Fabricant Hynix Semiconductor 
Logo Hynix Semiconductor 





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16Mx64 bits
PC133 SDRAM Unbuffered DIMM
based on 8Mx16 SDRAM with LVTTL, 4 banks & 4K Refresh
HYM71V16635HCT6 Series
DESCRIPTION
The Hynix HYM71V16635HCT6 Series are 16Mx64bits Synchronous DRAM Modules. The modules are composed of eight 8Mx16bits
CMOS Synchronous DRAMs in 400mil 54pin TSOP-II package, one 2Kbit EEPROM in 8pin TSSOP package on a 168pin glass-epoxy
printed circuit board. Two 0.33uF and one 0.1uF decoupling capacitors per each SDRAM are mounted on the PCB.
The Hynix HYM71V16635HCT6 Series are Dual In-line Memory Modules suitable for easy interchange and addition of 128Mbytes
memory. The Hynix HYM71V16635HCT6 Series are fully synchronous operation referenced to the positive edge of the clock . All
inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high
bandwidth.
FEATURES
• PC133/PC100MHz support
• SDRAM internal banks : four banks
• 168pin SDRAM Unbuffered DIMM
• Module bank : two physical bank
• Serial Presence Detect with EEPROM
• Auto refresh and self refresh
• 1.25” (31.75mm) Height PCB with double sided com- • 4096 refresh cycles / 64ms
ponents
• Programmable Burst Length and Burst Type
• Single 3.3±0.3V power supply
- 1, 2, 4 or 8 or Full page for Sequential Burst
• All device pins are compatible with LVTTL interface
- 1, 2, 4 or 8 for Interleave Burst
• Data mask function by DQM
• Programmable CAS Latency ; 2, 3 Clocks
ORDERING INFORMATION
Part No.
HYM71V16M635HCT6-K
HYM71V16M635HCT6-H
HYM71V16M635HCLT6-K
HYM71V16M635HCLT6-H
Clock
Frequency
133MHz
Internal
Bank
4 Banks
Ref.
4K
Power
Normal
Low Power
SDRAM
Package
Plating
TSOP-II
Gold
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev. 0.5 / Mar. 2003
2

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