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PDF SCC2698B Data sheet ( Hoja de datos )
| Número de pieza | SCC2698B | |
| Descripción | Enhanced octal universal asynchronous receiver/transmitter Octal UART | |
| Fabricantes | NXP Semiconductors | |
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INTEGRATED CIRCUITS
SCC2698B
Enhanced octal universal asynchronous
receiver/transmitter (Octal UART)
Product specification
Supersedes data of 1998 Sep 04
2000 Jan 31
Philips
Semiconductors
1 page  
www.DPahtailiSphseSeet4mUic.oconmductors
Enhanced octal universal asynchronous
receiver/transmitter (Octal UART)
Product specification
SCC2698B
PIN DESCRIPTION
MNEMONIC
D0–D7
PIN
NO.
8–13,
16, 17
CEN
18
WRN
19
RDN
22
A0–A5
RESET
23, 25,
27, 29,
31, 32
15
INTRAN–
INTRDN
X1/CLK
35, 36,
46, 47
7
X2
RxDa–RxDh
TxDa–TxDh
MPOa–MPOh
6
3, 56,
83, 57,
79, 58,
75, 59
1, 41,
81, 49,
74, 52,
73, 55
72, 43,
71, 51,
69, 53,
67, 54
MPI0a–MPI0h
33, 34,
37, 39,
61, 63,
76, 77
TYPE
NAME AND FUNCTION
I/O Data Bus: Active–High 8-bit bidirectional 3-State data bus. Bit 0 is the LSB and bit 7 is the MSB. All
data, command, and status transfers between the CPU and the Octal UART take place over this bus.
The direction of the transfer is controlled by the WRN and RDN inputs when the CEN input is low.
When the CEN input is High, the data bus is in the 3-State condition.
I Chip Enable: Active-Low input. When Low, data transfers between the CPU and the Octal UART are
enabled on D0–D7 as controlled by the WRN, RDN and A0–A5 inputs. When CEN is High, the Octal
UART is effectively isolated from the data bus and D0–D7 are placed in the 3-State condition.
I Write Strobe: Active-Low input. A Low on this pin while CEN is Low causes the contents of the data
bus to be transferred to the register selected by A0–A5. The transfer occurs on the trailing (rising)
edge of the signal.
I Read Strobe: Active-Low input. A Low on this pin while CEN is Low causes the contents of the
register selected by A0–A5 to be placed on the data bus. The read cycle begins on the leading
(falling) edge of RDN.
I Address Inputs: Active-High address inputs to select the Octal UART registers for read/write
operations.
I Reset: Master reset. A High on this pin clears the status register (SR), clears the interrupt mask
register (IMR), clears the interrupt status register (ISR), clears the output port configuration register
(OPCR), places the receiver and transmitter in the inactive state causing the TxD output to go to the
marking (High) state, and stops the counter/timer. Clears power-down mode and interrupts. Clears
Test Modes, sets MR pointer to MR1.
O Interrupt Request: This active-Low open drain output is asserted on occurrence of one or more of
eight maskable interrupting conditions. The CPU can read the interrupt status register to determine
the interrupting condition(s). These pins require a pullup device and may be wire ORed.
I Crystal 1: Crystal or external clock input. When using the crystal oscillator, this pin serves as the
connection for one side of the crystal. If a crystal is not used, an external clock is supplied at this
input. An external clock (or crystal) is required even if the internal baud rate generator is not utilized.
This clock is used to drive the internal baud rate generator, as an optional input to the timer/counter,
and to provide other clocking signals required by the chip.
I Crystal 2: Connection for other side of crystal. If an external source is used instead of a crystal, this
connection should be left open (see Figure 9).
I Receiver Serial Data Input: The least significant bit is received first. If external receiver clock is
specified, this input is sampled on the rising edge of the clock. If internal clock is used, the RxD input
is sampled on the rising edge of the RxC1x signal as seen on the MPO pin.
O Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the
marking (High) condition when the transmitter is idle or disabled and when the Octal UART is
operating in local loopback mode. If external transmitter is specified, the data is shifted on the falling
edge of the transmitter clock. If internal clock is used, the TxD output changes on the falling edge of
the TxC1x signal as seen on the MPO pin.
O Multi-Purpose Output: Each of the four DUARTS has two MPO pins (one per UART). One of the
following eight functions can be selected for this output pin by programming the OPCR (output port
configuration register). Note that reset conditions MPO pins to RTSN.
RTSN – Request to send active-Low output. This output is asserted and negated via the command
register. By appropriate programming of the mode registers, (MR1[7])=1 RTSN can be programmed to
be automatically reset after the character in the transmitter is completely shifted or when the receiver
FIFO and shift register are full. RTSN is an internal signal which normally represents the condition of
the receiver FIFO not full, i.e., the receiver can request more data to be sent. However, it can also be
controlled by the transmitter empty and the commands 8h and 9h written to the CR (command
register).
C/TO – The counter/timer output.
TxC1X – The 1X clock for the transmitter.
TxC16X – The 16X clock for the transmitter.
RxC1X – The 1X clock for the receiver.
RxC16X – The 16X clock for the receiver.
TxRDY – Transmitter holding register empty signal.
RxRDY/FFULL – Receiver FIFO not empty/full signal.
I Multi-Purpose Input 0: This pin (one in each UART) is programmable. Its state can always be read
through the IPCR bit 0, or the IPR bit 0.
CTSN: By programming MR2[4] to a 1, this input controls the clear-to-send function for the
transmitter. It is active low. This pin is provided with a change-of-state detector.
2000 Jan 31
5
5 Page 
www.DPahtailiSphseSeet4mUic.oconmductors
Enhanced octal universal asynchronous
receiver/transmitter (Octal UART)
Product specification
SCC2698B
receiver indicating that the receiver is ready to receive data. It is
also active low and is, thus, called RTSN. RTSN is on pin MPO. A
receiver’s RTS output will usually be connected to the CTS input of
the associated transmitter. Therefore, one could say that RTS and
CTS are different ends of the same wire!
MR2(4) is the bit that allows the transmitter to be controlled by the
CTS pin ( MPI0). When this bit is set to one AND the CTS input is
driven high, the transmitter will stop sending data at the end of the
present character being serialized. It is usually the RTS output of
the receiver that will be connected to the transmitter’s CTS input.
The receiver will set RTS high when the receiver FIFO is full AND
the start bit of the fourth character is sensed. Transmission then
stops with four valid characters in the receiver. When MR2(4) is set
to one, CTSN must be at zero for the transmitter to operate. If
MR2(4) is set to zero, the MPI0 pin will have no effect on the opera-
tion of the transmitter.
MR1(7) is the bit that allows the receiver to control MPO. When
MPO is controlled by the receiver, the meaning of that pin will be
RTS. However, a point of confusion arises in that MPO may also be
controlled by the transmitter. When the transmitter is controlling this
pin, its meaning is not RTS at all. It is, rather, that the transmitter
has finished sending its last data byte. Programming the MPO pin
to be controlled by the receiver and the transmitter at the same time
is allowed, but would usually be incompatible.
RTS can also be controlled by the commands 1000 and 1001 in the
command register. RTS is expressed at the MP0 pin which is still an
output port. Therefore, the state of MP0 should be set low (either by
commands of the CR register or by writing to the Output Port Con-
figuration Register) for the receiver to generate the proper RTS sig-
nal. The logic at the output is basically a NAND of the MP0 bit
register and the RTS signal as generated by the receiver. When the
RTS flow control is selected via the MR1(7) bit the state of the MP0
register is not changed. Terminating the use of “Flow Control” (via
the MR registers) will return the MP0 pin to the control of the MP0
register.
Transmitter Disable Note
When the TxEMT bit is set the sequence of instructions: enable
transmitter — load transmit holding register — disable transmitter
will often result in nothing being sent. In the condition of the TxEMT
being set do not issue the disable until the TxRDY bit goes active
again after the character is loaded to the TxFIFO. The data is not
sent if the time between the end of loading the transmit holding reg-
ister and the disable command is less that 3/16 bit time in the 16x
mode. One bit time in the 1x mode.
This is sometimes the condition when the RS485 automatic “turn-
around” is enabled . It will also occur when only one character is to
be sent and it is desired to disable the transmitter immediately after
the character is loaded.
In general, when it is desired to disable the transmitter before the
last character is sent AND the TxEMT bit is set in the status register
be sure the TxRDY bit is active immediately before issuing the
transmitter disable instruction. (TxEMT is always set if the transmit-
ter has underrun or has just been enabled), TxRDY sets at the end
of the “start bit” time. It is during the start bit that the data in the
transmit holding register is transferred to the transmit shift register.
MULTI-PURPOSE INPUT PIN
The inputs to this unlatched 8-bit port for each block can be read by
the CPU, by performing a read operation as shown in Table 1. A
High input results in a logic one, while a Low input results in a logic
zero. When the input port pins are read on the 84-pin LLCC, they
will appear on the data bus in alternating pairs (i.e., DB0 = MP10a,
DB1 = MPI1a, DB2 = MPI0b, DB3 = MPI1b, DB4 = MPP1a, DB5 =
MPP2a, DB6 = MPP1b, DB7 = MPP2b. Although this example is
shown for input port ‘A’, all ports will have a similar order).
The MPI pin can be programmed as an input to one of several Octal
UART circuits. The function of the pin is selected by programming
the appropriate control register. Change-of-state detectors are
provided for MPI0 and MPI1 for each channel in each block. A
High-to-Low or Low-to-High transition of the inputs lasting longer
than 25 to 50µs sets the MPI change-of-state bit in the interrupt
status register. The bit is cleared via a command. The
change-of-state can be programmed to generate an interrupt to the
CPU by setting the corresponding bit in the interrupt mask register.
The input port pulse detection circuitry uses a 38.4KHz sampling
clock, derived from one of the baud rate generator taps. This
produces a sampling period of slightly more than 25µs (assuming a
3.6864MHz oscillator input). The detection circuitry, in order to
guarantee that a true change in level has occurred, requires two
successive samples be observed at the new logic level. As a
consequence, the minimum duration of the signal change is 25µs if
the transition occurs coincident with the first sample pulse. (The
50µs time refers to the condition where the change-of-state is just
missed and the first change of state is not detected until after an
additional 25µs.)
MULTI-PURPOSE I/O PINS
The multi-purpose pins (MPP) can be programmed as inputs or
outputs using OPCR[7]. When programmed as inputs, the functions
of the pins are selected by programming the appropriate control
registers. When programmed as outputs, the two MPP1 pins (per
block) will provide the transmitter ready (TxRDY) status for each
channel and the MPP2 pins will provide the receiver ready or FIFO
full (RxRDY/FFULL) status for each channel.
MULTI-PURPOSE OUTPUT PIN
This pin can be programmed to serve as a request-to-send output,
the counter/timer output, the output for the 1X or 16X transmitter or
receiver clocks, the TxRDY output or the RxRDY/FFULL output (see
OPCR [2:0] and OPCR [6:4] – MPO Output Select).
2000 Jan 31
11
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| PDF Descargar | [ Datasheet SCC2698B.PDF ] | |
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