PDF TAAD08JU2 Data sheet ( Hoja de datos )

Número de pieza	TAAD08JU2
Descripción	T1/E1/J1 ATM Processor
Fabricantes	Agere Systems
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No Preview Available ! www.DataSheet4U.com Preliminary Data Sheet August 18, 2003 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 1 Features s System-on-a-chip integrated circuit supports low- speed ATM access for next-generation wireless base transmission station (BTS), base station con- troller (BSC), node-B, radio network controller (RNC), and remote access concentrator (RAC) applications. s IC provides an integrated octal framer that sup- ports T1/E1/J1 formats. s Supports inverse multiplexing for ATM (IMA) over selected group and link mappings ranging from four two-link groups up to one eight-link group per ATM Forum AF-PHY-0086.001. s Integrates an ATM adaptation layer 2 (AAL2) seg- mentation and reassembly (SAR) function for sup- port of low-speed data or voice traffic per ITU I.363.2. s Provides AAL5 SAR functionality per ITU I.363.5. s Provides quality of service (QoS) connection iden- tifier (CID) multiplexing per ITU I.366.1. s Enables ATM layer user network interface (UNI) or IMA mode, selectable on a per-link basis for flexi- ble transport of delay critical voice and data traffic. s Guarantees QoS for a variety of traffic types (including delay-sensitive voice, real-time data, non-real-time data, and signaling information) through an advanced hierarchical three-level prior- ity scheduler and per-VC queueing. s Supports 2032 bidirectional AAL2 CIDs. s Supports 2032 bidirectional high-speed data con- nections or virtual circuits (VCs) via embedded context memory; filters control cells and accepts control cells via a host microprocessor interface. s On-board memory is used for connection manage- ment and queue data storage. No external memory is needed. s Software package includes the following: — Device manager source code (C-based device manager ready-to-use with host RTOS). — Setup file utility to provision TAAD08JU2. — Firmware for embedded controller (executable binary). — API reference manual available for device man- ager software. s Designed in 0.16 µm, low-power CMOS technology. 2 Physical s 3.3 V digital I/O compatibility; 1.5 V core power s 520 enhanced ball-grid array (EBGA) package s –40 oC to +85 oC temperature range 3 Standards ITU I.363.2, ITU I.363.5, ITU I.366.1, ITU I.366.2, ITU I.432, ITU I.361, ITU I.371, ITU G.703, ITU G.704, ITU G.804, ITU G.732, ITU G.706, ITU I.610, ITU G.775, ITU G.733, ITU G.735, ITU G.965, ITU O.162, ANSI® T1.403, ANSI T1.231, ATM Forum AF-PHY-0086.001 ATM Forum AF-PHY-0039.000 ATM Forum AF-TM-0121.000 ETS 300.417-1-1 1 page www.DatDaSahtaeeSt4hUe.ectom August 18, 2003 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 Table of Contents (continued) Contents Page 18.4.6 Queueing and Scheduling ......................................................................................................109 18.4.7 Modes .....................................................................................................................................109 18.4.8 User Data Types (UDT) and AAL Types ................................................................................. 110 18.4.9 UDT: ATM Cell ........................................................................................................................ 111 18.4.10 AAL Type: AAL0 ..................................................................................................................... 111 18.4.11 AAL Type: AAL2 ..................................................................................................................... 111 18.4.12 AAL2 Subtype: SPAAL2 (Single-Packet AAL2) ...................................................................... 112 18.4.13 CPS-AAL0 .............................................................................................................................. 113 18.4.14 AAL Type: AAL5 ..................................................................................................................... 113 18.4.15 UDT: Packet ATM (PATM)....................................................................................................... 114 18.4.16 UDT: HPF................................................................................................................................ 115 18.4.17 AAL Type: NPAAL (No Particular AAL)................................................................................... 116 18.4.18 Nonuser Data Types: ESI Messages ...................................................................................... 116 18.4.18.1 ESI Message Format ............................................................................................... 116 18.4.18.2 ESI Violation Code ................................................................................................... 117 18.4.18.3 ESI Packet Length ................................................................................................... 117 18.4.19 Service Types ......................................................................................................................... 117 18.4.20 CPS_SERVICE....................................................................................................................... 118 18.4.21 SEG_AAL2_SSSAR_SERVICE ............................................................................................. 119 18.4.22 SEG_AAL2_SSTED_SERVICE.............................................................................................. 119 18.4.23 SEG_AAL5_SERVICE............................................................................................................ 119 18.4.24 TRANSPARENT_SERVICE....................................................................................................120 18.4.25 REASS_AAL2_SSSAR_SERVICE .........................................................................................120 18.4.26 REASS_AAL2_SSTED_SERVICE .........................................................................................120 18.4.27 REASS_AAL5_SERVICE .......................................................................................................120 18.5 Provisioning ..........................................................................................................................................122 18.5.1 Some Notes on Terminology and Command Referencing......................................................122 18.5.2 System Interface.....................................................................................................................122 18.5.3 Port Table................................................................................................................................123 18.5.4 MEMI Shared Memory............................................................................................................124 18.5.4.1 MEMI-SM Provisioning Constraints..........................................................................125 18.5.4.2 VC Table...................................................................................................................125 18.5.4.3 AAL2 VC Table .........................................................................................................126 18.5.4.4 Connection Table .....................................................................................................127 18.5.4.5 Level 0 Queue Descriptor ........................................................................................129 18.5.4.6 ICID Table ................................................................................................................129 18.5.5 SQASE Shared Memory .........................................................................................................129 18.6 Configuration ........................................................................................................................................130 18.6.1 Connection and Channel Setup..............................................................................................130 18.6.1.1 AAL2 Data Flow (CPS/SSSAR/SSTED) ..................................................................133 18.6.1.2 CPS-AAL0 Data Flow...............................................................................................133 18.6.1.3 AAL0/AAL5 Data Flow..............................................................................................133 18.6.1.4 HPF Data Flow .........................................................................................................133 18.6.2 Configuration for QoS .............................................................................................................134 18.6.2.1 Packet Scheduling ...................................................................................................134 18.6.2.2 IL1Q Scheduler Algorithm ........................................................................................134 18.6.2.3 IL2Q Scheduler Algorithm ........................................................................................134 18.6.2.4 Latency Policing .......................................................................................................136 18.6.2.5 Latency-Sensitive Data Discard ...............................................................................136 18.6.2.6 Internal Queue Housekeeping .................................................................................136 18.6.2.7 Reference Clock Generation ....................................................................................136 18.6.2.8 Latency Timer Enable/Disable Functions.................................................................137 Agere Systems Inc. Agere Systems - Proprietary Use pursuant to Company instructions 5 5 Page www.DatDaSahtaeeSt4hUe.ectom August 18, 2003 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 4 Description TAAD08JU2 provides a flexible network-interface solution for next-generation applications in which efficient trans- port of narrowband voice and broadband data information is critical to guaranteeing network QoS for the user and transmission efficiency for the network operator. Constructed using Agere’s 0.16 µm CMOS technology, the chip has an integrated octal framer, IMA processor, cell scheduler and router, and AAL2/5 SAR functions. TAAD08JU2 operates in either UNI or IMA mode (selectable on a per-span line basis). The complete AF-PHY- 0086.001 management information base (MIB) is supported. Flexible provisioning of link and group combinations enables a mix of IMA and UNI mappings to various AAL services. Support for AAL2 is provided via an AAL/CPS function that maps/demaps variable-sized CPS packets to/from ATM-SDU. A total of 2032 bidirectional CIDs are supported. These CIDs can be transported within a programma- ble number of VCs per direction. TAAD08JU2 supports up to 124 AAL2 VCs, which may be allocated between ingress and egress traffic. Support for high-speed data switching is provided whereby AAL5 VCs are routed through to the system interface toward their destinations. TAAD08JU2 provides support for up to 2032 bidirectional AAL5 VCs via an internal con- text memory. TAAD08JU2 provides the following: ! Integrated policing ! F4/F5 operations, administration, and maintenance (OAM) ! Cell processing ! Statistics collection for performance monitoring Communication with TAAD08JU2 is accomplished through a 32-bit microprocessor interface. The system interface is through two choices: a UTOPIA 2 interface with support for both 8-bit and 16-bit data bus width and a UTOPIA- derived packet interface with support for both 8-bit and 16-bit data bus widths. TAAD08JU2 provides a complete ATM access function from AAL/CPS mapping functions (for AAL2 and 5) through ATM/TC/PHY layers. The highly integrated, flexible architecture results in unified OAM features, simpler operation, and best-in-class operation with respect to area, power, and function. Agere Systems Inc. Agere Systems - Proprietary 11 11 Page

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