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PDF E8870IO Data sheet ( Hoja de datos )
| Número de pieza | E8870IO | |
| Descripción | Intel E8870IO Server I/o Hub | |
| Fabricantes | Intel Corporation | |
| Logotipo |  |
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Intel® E8870IO Server I/O Hub (SIOH)
Datasheet
Product Features
s Scalability Port (SP):
— Two SPs with 3.2 GB/s peak bandwidth
per direction per SP.
— Bi-directional SPs for a total bandwidth
of 12.8 GB/s.
s Four Hub Interface 2.0 Ports:
— For connecting to Intel® 82870P2 PCI/
PCI-X 64-bit Hub 2 (P64H2).
— 16-bit, 533 MHz interface.
— 1 GB/s peak data rate.
s One Hub Interface 1.5 Port:
— For connecting to Intel® 82801DB.
Legacy I/O Controller Hub 4 (ICH4).
— 8-bit, 266 MHz interface.
— 266 MB/s peak data rate.
s Supports peer-to-peer write traffic between
Hub Interface Ports.
s Dedicated read cache for each Hub
Interface Port:
— 32 128-byte cache lines.
— Dedicated prefetch engines for Hub
Interface 2.0 ports.
s Supports caching of frequently used and
prefetched data residing in main memory.
s 64-line write cache.
s Aggressive prefetching algorithm
optimized for PCI-X functionality
supported by the 82870P2 component:
— Utilizing enhanced features such as
read-streaming, and prefetch horizon.
s Supports multiple unordered inbound
traffic streams:
— Two unordered streams per Hub
Interface 2.0 port.
— One stream for the Hub Interface 1.5
port.
s System Management Bus (SMBus) 2.0
slave interface for server management with
Packet Error Checking.
s Reliability, Availability, and Serviceability
(RAS):
— Sideband access to configuration
registers via SMBus SMBus or JTAG.
— End-to-end ECC for all interfaces.
— Fault detection and logging.
— Signal connectivity testing via.
boundary scan.
s Packaging:
— 42.5 mm x 42.5 mm
— 1012-pin organic LAN grid array
(OLGA) package-2B.
Document Number: 251111-001
August 2002
1 page  
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5.5 JTAG Test Access Port ......................................................................................5-2
5.6 SMBus Clocking .................................................................................................5-2
5.7 Spread Spectrum Support..................................................................................5-2
5.8 No Stop Clock or Thermal Shutdown .................................................................5-2
5.9 Deterministic Systems........................................................................................5-3
6 Reset ...............................................................................................................................6-1
6.1 Reset Sequence Overview.................................................................................6-1
6.2 Power-Up Sequence ..........................................................................................6-2
6.2.1 PWRGOOD Deasserted........................................................................6-2
6.2.2 PWRGOOD Assertion ...........................................................................6-2
6.2.3 First RESETI# Deassertion ...................................................................6-2
6.3 Hard Reset .........................................................................................................6-2
6.3.1 Hard Reset Assertion ............................................................................6-3
6.3.2 Hard Reset Deassertion ........................................................................6-3
6.3.3 Non-Existent Hub Interface Devices .....................................................6-3
6.4 Reset Signals .....................................................................................................6-4
6.4.1 PWRGOOD ...........................................................................................6-4
6.4.2 RESETI# ...............................................................................................6-4
6.4.3 RESET66# ............................................................................................6-4
6.4.4 DET .......................................................................................................6-4
7 Reliability, Availability and Serviceability (RAS) ..............................................................7-1
7.1 Data Integrity ......................................................................................................7-1
7.1.1 End-to-End Error Correction..................................................................7-1
7.1.2 Error Reporting......................................................................................7-2
7.1.3 Interface Details ....................................................................................7-4
7.1.4 Time-Out ...............................................................................................7-5
8 Electrical Specifications...................................................................................................8-1
8.1 Non-Operational Maximum Rating .....................................................................8-1
8.2 Operational Power Delivery Specification ..........................................................8-1
8.3 Scalability Port (SP) Signal Group .....................................................................8-2
8.4 Hub Interface 2.0 (HI 2.0) Signal Group.............................................................8-3
8.4.1 Hub Interface 2.0 DC Specifications .....................................................8-3
8.5 Hub Interface 1.5 (HI 1.5) Signal Group.............................................................8-4
8.5.1 HI 1.5 Signal Groups .............................................................................8-4
8.5.2 Hub Interface 1.5 DC Specifications .....................................................8-4
8.6 Analog Inputs .....................................................................................................8-5
8.6.1 Hub Interface Impedance Compenstation (RCOMP) ............................8-5
8.6.2 Hub Interface Vref/Vswing Decoupling..................................................8-6
8.7 SMBus and TAP Signal Group...........................................................................8-6
8.7.1 SMBus and TAP DC Specifications ......................................................8-7
8.7.2 SMBus and TAP AC Specifications.......................................................8-8
8.7.3 SMBus and TAP AC Timing Waveforms...............................................8-9
8.8 Miscellaneous Signal Group...............................................................................8-9
8.8.1 Miscellaneous Signal DC Specifications .............................................8-10
8.8.2 Miscellaneous Signal AC Specifications .............................................8-11
8.9 Clock Signal Groups.........................................................................................8-12
8.9.1 AC Specification ..................................................................................8-13
Intel® E8870IO Server I/O Hub (SIOH) Datasheet
v
5 Page 
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Refer to Figure 1-2 and Figure 1-3.
Figure 1-2. SIOH Interfaces
Introduction
Write Cache
Hub Interface
Rev. 1.5
Compliant
Read
Cache
Traffic Routing
Read
Cache
Read
Cache
Read
Cache
Read
Cache
SIOH
Hub Interface
(8-bit)
Hub Interface
Rev. 2.0
Compliant
001125
The SIOH is responsible for routing traffic between the different Hub Interfaces and Scalability
Ports.
Figure 1-3. SIOH Functional Blocks
Scalability Port Interface
Hub Interface
Rev. 1.5
Compliant
Config
Registers
Internal Interconnect
Hub Interface
Hub Interface
(8-bit)
Hub Interface
Hub Interface
Hub Interface
Hub Interface
SIOH
Hub Interface
Rev. 2.0
Compliant
Intel® E8870IO Server I/O Hub (SIOH) Datasheet
001152
1-3
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