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PDF 26LV800BTC Data sheet ( Hoja de datos )
| Número de pieza | 26LV800BTC | |
| Descripción | MX26LV800BTC | |
| Fabricantes | Macronix International | |
| Logotipo |  |
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FEATURES
MX26LV800T/B
Macronix NBitTM Memory Family
8M-BIT [1Mx8/512K x16] CMOS SINGLE VOLTAGE
3V ONLY HIGH SPEED eLiteFlashTM MEMORY
• Extended single - supply voltage range 3.0V to 3.6V
• 1,048,576 x 8/524,288 x 16 switchable
• Single power supply operation
- 3.0V only operation for read, erase and program
operation
• Fast access time: 55/70ns
• Low power consumption
- 30mA maximum active current
- 30uA typical standby current
• Command register architecture
- Byte/word Programming (55us/70us typical)
- Sector Erase (Sector structure 16K-Bytex1,
8K-Bytex2, 32K-Bytex1, and 64K-Byte x15)
• Auto Erase (chip & sector) and Auto Program
- Automatically erase any combination of sectors with
Erase verify capability.
- Automatically program and verify data at specified
address
• Status Reply
- Data# polling & Toggle bit for detection of program
and erase operation completion.
• Ready/Busy# pin (RY/BY#)
- Provides a hardware method of detecting program or
erase operation completion.
• 2,000 minimum erase/program cycles
• Latch-up protected to 100mA from -1V to VCC+1V
• Boot Sector Architecture
- T = Top Boot Sector
- B = Bottom Boot Sector
• Package type:
- 48-pin TSOP
- 48-ball CSP
• Compatibility with JEDEC standard
- Pinout and software compatible with single-power
supply Flash
• 20 years data retention
GENERAL DESCRIPTION
The MX26LV800T/B is a 8-mega bit high speed Flash
memory organized as 1M bytes of 8 bits or 512K words
of 16 bits. MXIC's high speed Flash memories offer the
most cost-effective and reliable read/write non-volatile
random access memory. The MX26LV800T/B is pack-
aged in 48-pin TSOP, and 48-ball CSP. It is designed to
be reprogrammed and erased in system or in standard
EPROM programmers.
The standard MX26LV800T/B offers access time as fast
as 55ns, allowing operation of high-speed microproces-
sors without wait states. To eliminate bus contention,
the MX26LV800T/B has separate chip enable (CE#) and
output enable (OE#) controls.
MXIC's high speed Flash memories augment EPROM
functionality with in-circuit electrical erasure and program-
ming. The MX26LV800T/B uses a command register to
manage this functionality. The command register allows
for 100% TTL level control inputs and fixed power sup-
ply levels during erase and programming, while main-
taining maximum EPROM compatibility.
MXIC high speed Flash technology reliably stores
memory contents even after 2,000 erase and program
cycles. The MXIC cell is designed to optimize the erase
and programming mechanisms. In addition, the combi-
nation of advanced tunnel oxide processing and low in-
ternal electric fields for erase and program operations
produces reliable cycling. The MX26LV800T/B uses a
3.0V~3.6V VCC supply to perform the High Reliability
Erase and auto Program/Erase algorithms.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up pro-
tection is proved for stresses up to 100 milliamperes on
address and data pin from -1V to VCC + 1V.
P/N:PM1007
REV. 1.3, APR. 13, 2005
1
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BLOCK DIAGRAM
MX26LV800T/B
CE#
OE#
WE#
RESET#
CONTROL
INPUT
LOGIC
PROGRAM/ERASE
HIGH VOLTAGE
WRITE
STATE
MACHINE
(WSM)
A0-A18
ADDRESS
LATCH
AND
BUFFER
MX26LV800T/B
FLASH
ARRAY
ARRAY
SOURCE
HV
Y-PASS GATE
STATE
REGISTER
COMMAND
DATA
DECODER
SENSE
AMPLIFIER
PGM
DATA
HV
PROGRAM
DATA LATCH
COMMAND
DATA LATCH
Q0-Q15/A-1
I/O BUFFER
P/N:PM1007
REV. 1.3, APR. 13, 2005
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MX26LV800T/B
nal reset operation is complete, which requires a time of
tREADY (during Embedded Algorithms).The system can
thus monitor RY/BY# to determine whether the reset
operation is complete. If RESET# is asserted when a
program or erase operation is completed within a time of
tREADY (not during Embedded Algorithms). The sys-
tem can read data tRH after the RESET# pin returns to
VIH.
Refer to the AC Characteristics tables for RESET#
parameters and to Figure 22 for the timing diagram.
READ/RESET COMMAND
The read or reset operation is initiated by writing the
read/reset command sequence into the command reg-
ister. Microprocessor read cycles retrieve array data.
The device remains enabled for reads until the command
register contents are altered.
If program-fail or erase-fail happen, the write of F0H will
reset the device to abort the operation. A valid com-
mand must then be written to place the device in the
desired state.
SILICON-ID READ COMMAND
High speed Flash memories are intended for use in ap-
plications where the local CPU alters memory contents.
As such, manufacturer and device codes must be ac-
cessible while the device resides in the target system.
PROM programmers typically access signature codes
by raising A9 to a high voltage (VID). However, multi-
plexing high voltage onto address lines is not generally
desired system design practice.
The MX26LV800T/B contains a Silicon-ID-Read opera-
tion to supple traditional PROM programming methodol-
ogy. The operation is initiated by writing the read silicon
ID command sequence into the command register. Fol-
lowing the command write, a read cycle with A1=VIL,
A0=VIL retrieves the manufacturer code of C2H/00C2H.
A read cycle with A1=VIL, A0=VIH returns the device
code of DAH/22DAH for MX26LV800T, 5BH/225BH for
MX26LV800B.
SET-UP AUTOMATIC CHIP/SECTOR ERASE
COMMANDS
Chip erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
"set-up" command 80H. Two more "unlock" write cy-
cles are then followed by the chip erase command 10H
or sector erase command 30H.
The Automatic Chip Erase does not require the device
to be entirely pre-programmed prior to executing the Au-
tomatic Chip Erase. Upon executing the Automatic Chip
Erase, the device will automatically program and verify
the entire memory for an all-zero data pattern. When the
device is automatically verified to contain an all-zero
pattern, a self-timed chip erase and verify begin. The
erase and verify operations are completed when the data
on Q7 is "1" at which time the device returns to the
Read mode. The system is not required to provide any
control or timing during these operations.
When using the Automatic Chip Erase algorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved for the memory array
(no erase verification command is required).
If the Erase operation was unsuccessful, the data on
Q5 is "1" (see Table 8), indicating the erase operation
exceed internal timing limit.
The automatic erase begins on the rising edge of the
last WE# or CE# pulse, whichever happens first in the
command sequence and terminates when the data on
Q7 is "1" at which time the device returns to the Read
mode, or the data on Q6 stops toggling for two consecu-
tive read cycles at which time the device returns to the
Read mode.
P/N:PM1007
REV. 1.3, APR. 13, 2005
11
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