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PDF HD407A4359 Data sheet ( Hoja de datos )
| Número de pieza | HD407A4359 | |
| Descripción | (HD404358 Series) 4-Bit Microcomputer | |
| Fabricantes | Renesas Technology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de HD407A4359 (archivo pdf) en la parte inferior de esta página. Total 70 Páginas | ||
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To all our customers
Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand
names are mentioned in the document, these names have in fact all been changed to Renesas
Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and
corporate statement, no changes whatsoever have been made to the contents of the document, and
these changes do not constitute any alteration to the contents of the document itself.
Renesas Technology Home Page: http://www.renesas.com
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
1 page  
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Pin Arrangement
HD404358 Series
RA 1
R00/SCK
R01/SI
R02/SO
R03/TOC
TEST
RESET
OSC1
OSC2
GND
AVSS
R30/AN0
R31/AN1
R32/AN2
R33/AN3
R40/AN4
R41/AN5
R42/AN6
R43/AN7
AV CC
V CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
DP-42S
42 R23
41 R22
40 R21
39 R20
38 R13
37 R12
36 R11
35 R10
34 R83
33 R82
32 R81
31 R80
30 D8
29 D7
28 D6
27 D5
26 D4/STOPC
25 D3/BUZZ
24 D2/EVNB
23 D1/INT1
22 D0/INT0
TEST
RESET
OSC1
OSC2
GND
AVSS
R30/AN0
R31/AN1
R32/AN2
R33/AN3
R40/AN4
1
2
3
4
5
6
7
8
9
10
11
FP-44A
33 R12
32 R11
31 R10
30 R83
29 R82
28 R81
27 R80
26 D8
25 D7
24 D6
23 D5
3
5 Page 
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HD404358 Series
Bit 3
IM0
0 (IM of INT0)
Bit 2
IF0
(IF of INT0)
Bit 1
RSP
(Reset SP bit)
1
IMTA
(IM of timer A)
IFTA
(IF of timer A)
IM1
(IM of INT1)
Bit 0
IE
(Interrupt
enable flag)
IF1
(IF of INT1)
$000
$001
2
IMTC
(IM of timer C)
IFTC
(IF of timer C)
IMTB
(IM of timer B)
IFTB
(IF of timer B)
$002
IMS
3 (IM of serial)
IFS
(IF of serial)
IMAD
(IM of A/D)
IFAD
(IF of A/D)
$003
Interrupt control bits area
Bit 3
32 Not used
RAME
33 (RAM enable
flag)
34
35
Bit 2
ADSF
(A/D start flag)
IAOF
(IAD off flag)
Bit 1
WDON
(Watchdog
on flag)
ICEF
(Input capture
error flag)
Bit 0
Not used
$020
ICSF
(Input capture
status flag)
$021
Not used
$022
$023
Register flag area
IF: Interrupt request flag
IM: Interrupt mask
IE: Interrupt enable flag
SP: Stack pointer
Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas
IE
IM
IAOF
IF
ICSF
ICEF
RAME
RSP
WDON
ADSF
Not used
SEM/SEMD
Allowed
Not executed
Not executed
Allowed
Allowed
Not executed
REM/REMD
Allowed
Allowed
Allowed
Not executed
Inhibited
Not executed
TM/TMD
Allowed
Allowed
Inhibited
Inhibited
Allowed
Inhibited
Note: WDON is reset by MCU reset or by STOPC enable for stop mode cancellation.
The REM or REMD instuction must not be executed for ADSF during A/D conversion.
If the TM or TMD instruction is executed for the inhibited bits or non-existing bits,
the value in ST becomes invalid.
Figure 4 Usage Limitations of RAM Bit Manipulation Instructions
9
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| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet HD407A4359.PDF ] | |
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