AD5439 Datasheet PDF - Analog Devices
| Part Number | AD5439 | |
| Description | (AD54x9) Bandwidth Multiplying DACs | |
| Manufacturers | Analog Devices | |
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FEATURES
10 MHz multiplying bandwidth
50 MHz serial interface
2.5 V to 5.5 V supply operation
±10 V reference input
Pin compatible 8-, 10-, and 12-bit DACs
Extended temperature range: −40°C to +125°C
16-lead TSSOP package
Guaranteed monotonic
Power-on reset
Daisy-chain mode
Readback function
0.5 µA typical current consumption
APPLICATIONS
Portable battery-powered applications
Waveform generators
Analog processing
Instrumentation applications
Programmable amplifiers and attenuators
Digitally controlled calibration
Programmable filters and oscillators
Composite video
Ultrasound
Gain, offset, and voltage trimming
Dual 8-,10-,12-Bit High Bandwidth
Multiplying DACs with Serial Interface
AD5429/AD5439/AD5449
VDD
SYNC
SCLK
SDIN
SDO
CLR
FUNCTIONAL BLOCK DIAGRAM
VREFA
AD5429/AD5439/AD5449
RFB
R
SHIFT
REGISTER
INPUT
REGISTER
DAC
REGISTER
8-/10-/12-BIT
R-2R DAC A
POWER-ON
RESET
INPUT
REGISTER
LDAC
DAC
REGISTER
8-/10-/12-BIT
R-2R DAC B
LDAC
Figure 1.
VREFB
RFB
R
RFBA
IOUT1A
IOUT2A
IOUT1B
IOUT2B
RFBB
GENERAL DESCRIPTION
The AD5429/AD5439/AD54491 are CMOS 8-, 10-, and 12-bit
dual-channel current output digital-to-analog converters,
respectively. These devices operate from a 2.5 V to 5.5 V power
supply, making them suited to battery-powered and other
applications.
The applied external reference input voltage (VREF) determines
the full-scale output current. An integrated feedback resistor
(RFB) provides temperature tracking and full-scale voltage
output when combined with an external current-to-voltage
precision amplifier.
These DACs utilize a double-buffered, 3-wire serial interface
that is compatible with SPI®, QSPI™, MICROWIRE™, and most
DSP interface standards. In addition, a serial data out pin (SDO)
allows daisy-chaining when multiple packages are used. Data
readback allows the user to read the contents of the DAC
register via the SDO pin. On power-up, the internal shift
register and latches are filled with zeros and the DAC outputs
are at zero scale.
As a result of manufacture on a CMOS submicron process,
these parts offer excellent 4-quadrant multiplication character-
istics, with large signal multiplying bandwidths of 10 MHz.
The AD5429/AD5439/AD5449 DAC are available in 16-lead
TSSOP packages.
1 US Patent Number 5,689,257.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
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AD5429/AD5439/AD5449
TIMING CHARACTERISTICS
VDD = 2.5 V to 5.5 V, VREF = 5 V, IOUT2 = 0 V. All specifications TMIN to TMAX, unless otherwise noted.
See Figure 2 and Figure 3. Temperature range for Y version is −40°C to +125°C. Guaranteed by design and characterization, not subject to
production test. All input signals are specified with tr = tf = ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
Table 2.
Parameter
fSCLK
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t122
Limit at TMIN, TMAX
50
20
8
8
13
5
4
5
30
0
12
10
25
60
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Conditions/Comments1
Max clock frequency
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
Data setup time
Data hold time
SYNC rising edge to SCLK falling edge
Minimum SYNC high time
SCLK falling edge to LDAC falling edge
LDAC pulse width
SCLK falling edge to LDAC rising edge
SCLK active edge to SDO valid, strong SDO driver
SCLK active edge to SDO valid, weak SDO driver
1 Falling or rising edge as determined by the control bits of the serial word. Strong or weak SDO driver selected via the control register.
2 Daisy-chain and readback modes cannot operate at maximum clock frequency. SDO timing specifications are measured with a load circuit, as shown in Figure 4.
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| Information | Total 30 Pages | |
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