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PDF AD5762R Data sheet ( Hoja de datos )
| Número de pieza | AD5762R | |
| Descripción | Bipolar Voltage Output DACs Preliminary | |
| Fabricantes | Analog Devices | |
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Preliminary Technical Data
Complete Dual, 16-Bit, High Accuracy,
Serial Input, Bipolar Voltage Output DACs
AD5762R
FEATURES
Complete dual, 16-bit digital-to-analog
converters (DACs)
Programmable output range: ±10 V, ±10.2564 V,
or ±10.5263 V
±1 LSB max INL error, ±1 LSB max DNL error
Low noise: 60 nV/√Hz
Settling time: 10 µs max
Integrated reference buffers
Internal reference: 10 ppm/°C
On-chip die temperature sensor
Output control during power-up/brownout
Programmable short-circuit protection
Simultaneous updating via LDAC
Asynchronous CLR to zero code
Digital offset and gain adjust
Logic output control pins
DSP-/microcontroller-compatible serial interface
Temperature range: −40°C to +85°C
iCMOS™ process technology1
APPLICATIONS
Industrial automation
Open-/closed-loop servo control
Process control
Data acquisition systems
Automatic test equipment
Automotive test and measurement
High accuracy instrumentation
GENERAL DESCRIPTION
The AD5762R is a dual, 16-bit, serial input, bipolar voltage
output digital-to-analog converter that operates from supply
voltages of ±11.4 V up to ±16.5 V. Nominal full-scale output
range is ±10 V. The AD5762R provides integrated output
amplifiers, reference buffers and proprietary power-up/power-
down control circuitry. The parts also feature a digital I/O port,
which is programmed via the serial interface and an analog
temperature sensor. The part incorporates digital offset and
gain adjust registers per channel.
The AD5762R is a high performance converter that offers
guaranteed monotonicity, integral nonlinearity (INL) of ±1 LSB,
low noise, and 10 µs settling time. The AD5762R includes an
on-chip 5 V reference with a reference tempco of 10 ppm/°C
maximum. During power-up (when the supply voltages are
changing), VOUT is clamped to 0 V via a low impedance path.
The AD5762R uses a serial interface that operates at clock rates
of up to 30 MHz and is compatible with DSP and
microcontroller interface standards. Double buffering allows
the simultaneous updating of all DACs. The input coding is
programmable to either twos complement or offset binary
formats. The asynchronous clear function clears all DAC
registers to either bipolar zero or zero scale depending on the
coding used. The AD5762R is ideal for both closed-loop servo
control and open-loop control applications. The AD5762R is
available in a 32-lead TQFP, and offers guaranteed
specifications over the −40°C to +85°C industrial temperature
range. See Figure 1, the functional block diagram.
1 For analog systems designers within industrial/instrumentation equipment
OEMs who need high performance ICs at higher voltage levels, iCMOS is a
technology platform that enables the development of analog ICs capable of
30 V and operating at ±15 V supplies while allowing dramatic reductions in
power consumption and package size, and increased AC and DC
performance.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.
1 page  
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Preliminary Technical Data
AD5762R
Parameter
DIGITAL INPUTS3
VIH, Input High Voltage
VIL, Input Low Voltage
Input Current
Pin Capacitance
DIGITAL OUTPUTS (D0, D1, SDO)3
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
High Impedance Leakage Current
High Impedance Output Capacitance
DIE TEMPERATURE SENSOR3
Output Voltage at 25°C
Output Voltage Scale Factor
Output Voltage Range
Output Load Current
Power-On Time
POWER REQUIREMENTS
AVDD/AVSS
DVCC
Power Supply Sensitivity3
∆VOUT/∆ΑVDD
AIDD
AISS
DICC
Power Dissipation
C Grade2
2
0.8
±1
10
0.4
DVCC − 1
0.4
DVCC − 0.5
±1
5
1.4
5
1.175/1.9
200
80
11.4/16.5
2.7/5.25
−85
3.5
2.75
1.2
140
Unit
V min
V max
µA max
pF max
V max
V min
V max
V min
µA max
pF typ
V typ
mV/°C typ
V min/V max
µA max
ms typ
V min/V max
V min/V max
dB typ
mA/channel max
mA/channel max
mA max
mW typ
Test Conditions/Comments
DVCC = 2.7 V to 5.25 V, JEDEC compliant
Per pin
Per pin
DVCC = 5 V ± 5%, sinking 200 µA
DVCC = 5 V ± 5%, sourcing 200 µA
DVCC = 2.7 V to 3.6 V,
sinking 200 µA
DVCC = 2.7 V to 3.6 V,
sourcing 200 µA
SDO only
SDO only
Die temperature
−40°C to 105°C
Current source only
Outputs unloaded
Outputs unloaded
VIH = DVCC, VIL = DGND, 750 µA typ
±12 V operation output unloaded
2 Temperature range : -40°C to +85°C; typical at 25°C. Device functionality is guaranteed to +105°C with degraded performance.
3 Guaranteed by design and characterization; not production tested.
4 Output amplifier headroom requirement is 1.4 V minimum.
Rev. PrA | Page 5 of 33
5 Page 
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Preliminary Technical Data
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD5762R
SYNC
SCLK
SDIN
SDO
CLR
LDAC
D0
D1
32
1
8
9
PIN 1
INDICATOR
AD5762R
TOP VIEW
(Not to Scale)
25
24
17
16
NC
NC
VOUTA
AGNDA
AGNDB
VOUTB
NC
NC
Figure 6. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic
Description
1 SYNC
Active Low Input. This is the frame synchronization signal for the serial interface.
While SYNC is low, data is transferred in on the falling edge of SCLK.
2 SCLK
Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK.
This operates at clock speeds up to 30 MHz.
3 SDIN
Serial Data Input. Data must be valid on the falling edge of SCLK.
4 SDO
Serial Data Output. Used to clock data from the serial register in daisy-chain or
readback mode.
51 CLR1
Negative Edge Triggered Input. Asserting this pin sets the DAC registers to 0x0000.
6 LDAC
Load DAC. Logic input. This is used to update the DAC registers and consequently
the analog outputs. When tied permanently low, the addressed DAC register is
updated on the rising edge of SYNC. If LDAC is held high during the write cycle, the
DAC input register is updated but the output update is held off until the falling edge
of LDAC. In this mode, all analog outputs can be updated simultaneously on the
falling edge of LDAC. The LDAC pin must not be left unconnected.
7, 8 D0, D1
9 RSTOUT
D0 and D1 form a digital I/O port. The user can set up these pins as inputs or outputs
that are configurable and readable over the serial interface. When configured as
inputs, these pins have weak internal pull-ups to DVCC. When programmed as
outputs, D0 and D1 are referenced by DVCC and DGND.
Reset Logic Output. This is the output from the on-chip voltage monitor used in the
reset circuit. If desired, it can be used to control other system components.
10 RSTIN
Reset Logic Input. This input allows external access to the internal reset logic.
Applying a Logic 0 to this input clamps the DAC outputs to 0 V. In normal operation,
RSTIN should be tied to Logic 1. Register values remain unchanged.
11 DGND
Digital Ground Pin.
12 DVCC
Digital Supply Pin. Voltage ranges from 2.7 V to 5.25 V.
13, 31
14
AVDD
PGND
Positive Analog Supply Pins. Voltage ranges from 11.4 V to 16.5 V.
Ground Reference Point for Analog Circuitry.
15, 30
16
AVSS
ISCC
Negative Analog Supply Pins. Voltage ranges from –11.4 V to –16.5 V.
This pin is used in association with an optional external resistor to AGND to program
the short-circuit current of the output amplifiers. Refer to the Features section for
further details.
17 NC
No Internal Connection
18 NC
No Internal Connection
Rev. PrA | Page 11 of 33
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD5762R.PDF ] | |
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