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PDF ICS951901 Data sheet ( Hoja de datos )
| Número de pieza | ICS951901 | |
| Descripción | Programmable Frequency Generator & Integrated Buffers | |
| Fabricantes | ICS | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
ICS951901
Programmable Frequency Generator & Integrated Buffers for Pentium III Processor
Recommended Application:
Single chip clock solution for IA platform.
Output Features:
• 3 - CPU @ 2.5V
• 13 - SDRAM @ 3.3V
• 6 - PCI @3.3V,
• 2 - AGP @ 3.3V
• 1 - 48MHz, @3.3V fixed.
• 1 - 24/48MHz, @3.3V selectable by I2C
(Default is 24MHz)
• 2 - REF @3.3V, 14.318MHz.
Features:
• Programmable ouput frequency.
• Programmable ouput rise/fall time.
• Programmable SDRAM and CPU skew.
• Spread spectrum for EMI control typically
by 7dB to 8dB,
with programmable spread percentage.
• Watchdog timer technology to reset system
if over-clocking causes malfunction.
• Uses external 14.318MHz crystal.
• FS pins for frequency select
Skew Specifications:
• CPU - CPU: < 175ps
• SDRAM - SDRAM < 250ps (except SDRAM12)
• PCI - PCI: < 500ps
• CPU (early) - PCI: 1-4ns (typ. 2ns)
Pin Configuration
VDDA
1*(AGPSEL)REF0
1*(FS3)REF1
GND
X1
X2
VDDPCI
*(FS1)PCICLK_F
*(FS2)PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
GND
VDDAGP
AGPCLK0
AGPCLK1
GND
GND
*(FS0)48MHz
*(MODE)24_48MHz
VDD48
SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 VDDL
47 CPUCLK0
46 CPUCLK1
45 CPUCLK2
44 GND
43 VDDSDR
42 SDRAM0
41 SDRAM1
40 SDRAM2
39 GND
38 SDRAM3
37 SDRAM4
36 SDRAM5
35 VDDSDR
34 SDRAM6
33 SDRAM7
32 GND
31 SDRAM8/PD#
30 SDRAM9/SDRAM_STOP#
29 GND
28 SDRAM10/PCI_STOP#
27 SDRAM11/CPU_STOP#
26 SDRAM12
25 VDDSDR
48-Pin 300mil SSOP
* These inputs have a 120K pull down to GND.
1 These are double strength.
Block Diagram
PLL2
X1 XTAL
X2 OSC
PLL1
Spread
Spectrum
SDATA
SCLK
FS(3:0)
PD#
PCI_STOP#
CPU_STOP#
SDRAM_STOP#
MODE
AGP_SEL
Control
Logic
Config.
Reg.
/2
CPU
DIVDER
Stop
SDRAM
DIVDER
Stop
PCI
DIVDER
Stop
AGP
DIVDER
48MHz
24_48MHz
REF(1:0)
2
CPUCLK (2:0)
3
SDRAM (12:0)
13
PCICLK (4:0)
5
PCICLK_F
AGP (1:0)
2
Functionality
FS3 FS2 FS1
Bit2 Bit7 Bit6 Bit5
00 0 0
00 0 0
00 0 1
00 0 1
00 1 0
00 1 0
00 1 1
00 1 1
01 0 0
01 0 0
01 0 1
01 0 1
01 1 0
01 1 0
01 1 1
01 1 1
FS0 CPU SDRAM
Bit4 MHz MHz
0 66.67 66.67
1 66.67 100.00
0 66.67 133.34
1 75.00 75.00
0 83.31 83.31
1 90.00 90.00
0 95.00 95.00
1 100.00 66.67
0 100.00 100.00
1 100.00 133.34
0 105.00 105.00
1 112.00 112.00
0 117.99 117.99
1 124.09 124.09
0 133.34 100.00
1 133.34 133.34
PCI
MHz
33.33
33.33
33.33
37.50
33.32
30.00
31.67
33.33
33.33
33.33
35.00
33.60
35.40
31.02
33.33
33.33
AGP1
SEL=1
66.67
66.67
66.67
75.00
66.64
60.00
63.33
66.67
66.67
66.67
70.00
67.20
70.80
62.05
66.67
66.67
AGP0
SEL=0
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
0670B—07/15/04
1 page  
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ICS951901
Byte 6: Control , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Bit7 2,3 0 REF strength 0=1X, 1=2X
Bit6 45
CPUCLK2 - Stop - Control
0 0=CPU_STOP# will control CPUCLK2,
1=CPUCLK2 is free running even if CPU_STOP# is low
Bit5 -
X AGPSEL (Readback)
Bit4 -
X MODE (Readback)
Bit3 -
X CPU_STOP# (Readback)
Bit2 -
X PCI_STOP# (Readback)
Bit1 -
X SDRAM_STOP# (Readback)
Bit0 -
AGP Speed Toggle
0 0=AGPSEL (pin2) will be determined by latch input setting,
1=AGPSEL will be opposite of latch input setting
Byte 7: Vendor ID Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
-
-
-
-
-
-
PWD
DESCRIPTION
0 Reserved
0 Reserved
1 Reserved
0 Reserved
1 Reserved
0 Reserved
0 Reserved
1 Reserved
Byte 8: Byte Count and Read Back Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
-
-
-
-
-
-
PWD
DESCRIPTION
0 Reserved
0 Reserved
0 Reserved
0 Reserved
0 Reserved
1 Reserved
0 Reserved
0 Reserved
Byte 9: Watchdog Timer Count Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
Description
0
0 The decimal representation of these
0 8 bits correspond to 290ms or 1ms
1
0
the watchdog timer will wait before
it goes to alarm mode and reset the
frequency to the safe setting. Default
0 at power up is 16X 290ms = 4.6
0 seconds.
0
0670B—07/15/04
Byte 10: VCO Control Selection Bit &
Watchdog Timer Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
0
0
0
0
0
0
0
0
Description
0=Hw/B0 freq / 1=B11 & 12 freq
WD Enable 0=disable / 1=enable
WD Status 0=normal / 1=alarm
WD Safe Frequency, Byte 0 bit 2
WD Safe Frequency, FS3
WD Safe Frequency, FS2
WD Safe Frequency, FS1
WD Safe Frequency, FS0
Note: FS values in bit [0:4] will correspond to Byte 0 FS
values. Default safe frequency is same as 00000
entry in byte0.
5
5 Page 
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ICS951901
Electrical Characteristics - AGP
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
Output Impedance
Output Impedance
RDSP4B1
RDSN4B1
VO=VDD*(0.5)
VO=VDD*(0.5)
Output High Voltage
VOH4B IOH = -18 mA
Output Low Voltage
VOL4B IOL = 18 mA
Output High Current
IOH4B VOH = 2.0 V
Output Low Current
Rise Time1
Fall Time1
Duty Cycle1
Skew window1
Jitter Cyc-Cyc
IOL4B
tr4B
tf4B
dt4B
tsk1
tjcyc-cyc1
VOL = 0.8 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
1Guaranteed by design, not 100% tested in production.
MIN TYP MAX UNITS
12 55
12 55
2V
0.4 V
-19 mA
19 mA
0.5 1.5 2 ns
0.5 1.6 2 ns
45 52.3 55 %
55.5 175 ps
239 500 ps
Electrical Characteristics - REF
TA = 0 - 70°C; VDD = 3.3 V +/-5%;VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Output High Voltage VOH5
IOH = -12 mA
2.4
Output Low Voltage
VOL5
IOL = 9 mA
0.4
Output High Current
IOH5
VOH = 2.0 V
-22
Output Low Current
IOL5
VOL = 0.8 V
16
Rise Time1
tr5 VOL = 0.4 V, VOH = 2.4 V
1.8 4
Fall Time1
tf5 VOH = 2.4 V, VOL = 0.4 V
1.9 4
Duty Cycle1
dt5
VT = 50%
45 54.5 55
1Guaranteed by design, not 100% tested in production.
V
V
mA
mA
ns
ns
%
0670B—07/15/04
11
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet ICS951901.PDF ] | |
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