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PDF ICS951601 Data sheet ( Hoja de datos )

Número de pieza ICS951601
Descripción General Purpose Frequency Timing Generator
Fabricantes ICS 
Logotipo ICS Logotipo



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No Preview Available ! ICS951601 Hoja de datos, Descripción, Manual

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Integrated
Circuit
Systems, Inc.
ICS951601
Preliminary Product Preview
General Purpose Frequency Timing Generator
Recommended Application:
General Purpose Clock Generator
Output Features:
• 17 - PCI clocks selectable,
either 33.33MHz or 66.6MHz @ 3.3V
• 1 - 48MHz @ 3.3V
• 1 - REF @ 3.3V, 14.318MHz.
Features:
• Programable Spread spectrum precentage for EMI control
• Uses external 14.318MHz crystal
• Select pins for frequency select
Key Specifications:
• PCI – PCI output skew within same bank @ 33MHz: <170ps
• PCI – PCI output skew within same bank@ 66MHz: <340ps
• Cycle to Cycle Jitter PCI @ 33MHz: <200ps
• Cycle to Cycle Jitter PCI @ 66MHz: <200ps
• Cycle to Cycle Jitter 48MHz: <350ps
• Cycle to Cycle Jitter REF: <500ps
• Slew Rate: 1.5 - 4 V/ns. (PCI spec.)
Block Diagram
PLL2
48MHz
Pin Configuration
REF0
VDD
X1
X2
GND
SDATA
SCLK
GNDA
VDDA
SEL1A
PCI1A_0
PCI1A_1
VDD33
GND
PCI1A_2
PCI1A_3
GND
VDD33
PCI1A_4
PCI1A_5
VDD33
GND
PCI1A_6
PCI1A_7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 48MHz
47 GND
46 VDD48
45 SPREAD
44 VDDA
43 GNDA
42 SEL2B
41 PCI2B_2
40 PCI2B_1
39 GND
38 VDD66
37 PCI2B_0
36 SEL2A
35 PCI2A_2
34 PCI2A_1
33 VDD2A
32 GND
31 PCI2A_0
30 SEL1B
29 PCI1B_2
28 PCI1B_1
27 GND
26 VDD1B
25 PCI1B_0
48-pin SSOP
*120K ohm pull-up to VDD on indicated inputs.
X1 XTAL
X2 OSC
REF0
PLL1
Spread
Spectrum
PCI
DIVDER
8 PCI1A (7:0)
SDATA
SCLK
SELA (2:1)
SELB (2:1)
SPREAD
Control
Logic
Config.
Reg.
PCI
DIVDER
PCI
DIVDER
PCI
DIVDER
0663B—09/04/03
3 PCI2A (2:0)
3 PCI1B (2:0)
3 PCI2B (2:0)
Power Groups:
VDDA = Analog Power
GNDA = Analog Ground
PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to
change without notice.

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ICS951601 pdf
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ICS951601
Preliminary Prouct Preview
Byte 1: PCI1A Stop Clocks Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
24
23
20
19
16
15
12
11
PWD
1
1
1
1
1
1
1
1
Description
PCI1A_7
PCI1A_6
PCI1A_5
PCI1A_4
PCI1A_3
PCI1A_2
PCI1A_1
PCI1A_0
Byte 2: PCI2A Stop Clocks
Register (1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
35
34
31
29
28
25
-
-
PWD
1
1
1
1
1
1
X
X
Description
PCI2A_2
PCI2A_1
PCI2A_0
PCI1B_2
PCI1B_1
PCI1B_0
Reserved
Reserved
Byte 3: PCI2B Stop Clocks Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
41
40
37
-
-
-
-
-
PWD
1
1
1
X
X
X
X
X
Description
PCI2B_2
PCI2B_1
PCI2B_0
Reserved
Reserved
Reserved
Reserved
Reserved
Byte 4: Reserved Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
48
1
-
-
-
-
-
-
PWD
1
1
X
X
X
X
X
X
Description
48MHz
REF0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Byte 5: Latched Input Read Back Register
(1= enable, 0 = disable)
Bit Pin # PWD
Description
Bit7 -
X SEL2B
Bit6 -
X SEL1B
Bit5 -
X SEL2A
Bit4 -
X SEL1A
Bit3 -
X Reserved
Bit2 -
X Reserved
Bit1 -
X Reserved
Bit0 -
X Reserved
Note: PWD = Power-Up Default
0663B—09/04/03
Byte 6: Reserved for Byte Count Register
(1= enable, 0 = disable)
Bit Pin # PWD
Description
Bit7 -
0
Reserved for read
byte count
Bit6 -
0 Reserved
Bit5 -
0 Reserved
Bit4 -
0 Reserved
Bit3 -
0 Reserved
Bit2 -
1 Reserved
Bit1 -
1 Reserved
Bit0 -
0 Reserved
5

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