PDF ICS951412 Data sheet ( Hoja de datos )

Número de pieza	ICS951412
Descripción	System Clock Chip
Fabricantes	ICS
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No Preview Available ! www.DataSheet4U.com Integrated Circuit Systems, Inc. ICS951412 System Clock Chip for ATI RS480 K8-based Systems Recommended Application: ATI RS480 systems using AMD K8 processors Output Features: • 3 - 14.318 MHz REF clocks • 1 - USB_48MHz USB clock • 1 - HyperTransport 66 MHz clock seed • 1 - PCI 33 MHz clock seed • 2 - Pairs of AMD K8 clocks • 6 - Pairs of SRC/PCI Express* clocks • 2 - Pairs of ATIG (SRC/PCI Express) clocks Features: • 2 - Programmable Clock Request pins for SRC clocks • Spread Spectrum for EMI reduction • Outputs may be disabled via SMBus • External crystal load capacitors for maximum frequency accuracy Pin Configuration X1 1 X2 2 VDD48 3 USB_48MHz 4 GND 5 NC 6 SCLK 7 SDATA 8 FS2 9 CLKREQA# 10 CLKREQB# 11 SRCCLKT7 12 SRCCLKC7 13 VDDSRC 14 GNDSRC 15 SRCCLKT6 16 SRCCLKC6 17 SRCCLKT5 18 SRCCLKC5 19 GNDSRC 20 VDDSRC 21 SRCCLKT4 22 SRCCLKC4 23 SRCCLKT3 24 SRCCLKC3 25 GNDSRC 26 ATIGCLKT1 27 ATIGCLKC1 28 56 VDDREF 55 GND 54 FS0/REF0 53 FS1/REF1 52 REF2 51 VDDPCI 50 PCICLK0 49 GNDPCI 48 VDDHTT 47 HTTCLK0 46 GNDHTT 45 CPUCLK8T0 44 CPUCLK8C0 43 VDDCPU 42 GNDCPU 41 CPUCLK8T1 40 CPUCLK8C1 39 VDDA 38 GNDA 37 IREF 36 GNDSRC 35 VDDSRC 34 SRCCLKT0 33 SRCCLKC0 32 VDDATI 31 GNDATI 30 ATIGCLKT0 29 ATIGCLKC0 Note: Pins preceeded by '' have a 120 Kohm Internal Pull Down resistor 56 Pin SSOP/TSSOP Power Groups Pin Number VDD GND 56 55 51 49 48 46 43 14, 21, 32,35 39 42 15, 20, 26,31,36 38 35 0883G—12/08/04 Description Xtal, REF PCICLK output HTTCLK output CPU Outputs SRC outputs Analog, CPU PLL USB_48MHz output Functionality FS2 FS1 00 00 01 01 10 10 11 FS0 0 1 0 1 0 1 1 CPU MHz Hi-Z X 180.00 220.00 100.00 133.33 200.00 HTT MHz Hi-Z X/3 60.00 73.12 66.66 66.66 66.66 PCI MHz Hi-Z X/6 30.00 36.56 33.33 33.33 33.33 *Other names and brands may be claimed as the property of others. 1 page www.DataSheet4U.com ICS951412 General SMBus serial interface information How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D2 (H) • ICS clock will acknowledge • Controller (host) sends the begining byte location = N • ICS clock will acknowledge • Controller (host) sends the data byte count = X • ICS clock will acknowledge • Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit How to Read: • Controller (host) will send start bit. • Controller (host) sends the write address D2 (H) • ICS clock will acknowledge • Controller (host) sends the begining byte location = N • ICS clock will acknowledge • Controller (host) will send a separate start bit. • Controller (host) sends the read address D3 (H) • ICS clock will acknowledge • ICS clock will send the data byte count = X • ICS clock sends Byte N + X -1 • ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). • Controller (host) will need to acknowledge each byte • Controllor (host) will send a not acknowledge bit • Controller (host) will send a stop bit Index Block Write Operation Controller (Host) ICS (Slave/Receiver) T starT bit Slave Address D2(H) WR WRite ACK Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK Byte N + X - 1 P stoP bit ACK 0883G—12/08/04 5 Index Block Read Operation Controller (Host) ICS (Slave/Receiver) T starT bit Slave Address D2(H) WR WRite ACK Beginning Byte = N ACK RT Repeat starT Slave Address D3(H) RD ReaD ACK ACK ACK Data Byte Count = X Beginning Byte N N Not acknowledge P stoP bit Byte N + X - 1 5 Page www.DataSheet4U.com ICS951412 Electrical Characteristics - K8 Push Pull Differential Pair TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =AMD64 Processor Test Load PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Rising Edge Rate Falling Edge Rate δV/δt δV/δt Measured at the AMD64 processor's test load. 0 V +/- 400 mV (differential measurement) 2 2 10 V/ns 10 V/ns Differential Voltage Change in VDIFF_DC Magnitude Common Mode Voltage VDIFF ∆VDIFF VCM 0.4 1.25 2.3 -150 150 Measured at the AMD64 processor's test load. (single-ended measurement) 1.05 1.25 1.45 V mV V Change in Common Mode Voltage ∆VCM -200 200 mV Jitter, Cycle to cycle tjcyc-cyc Measurement from differential wavefrom. Maximum difference of cycle time between 2 adjacent cycles. 0 100 200 ps Measured using the JIT2 software package with a Tek 7404 scope. Jitter, Accumulated tja TIE (Time Interval Error) measurement technique: -1000 1000 Sample resolution = 50 ps, Duty Cycle Sample Duration = 10 µs dt3 Measurement from differential wavefrom 45 53 Average value during switching Output Impedance RON transition. Used for determining series 15 35 55 termination value. Group Skew tsrc-skew Measurement from differential wavefrom 250 1Guaranteed by design and characterization, not 100% tested in production. 2 All accumulated jitter specifications are guaranteed assuming that REF is at 14.31818MHz 3 Spread Spectrum is off % Ω ps 1 1 1 1 1 1 1 1,2,3 1 1 1 0883G—12/08/04 11 11 Page

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