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PDF ICS951403 Data sheet ( Hoja de datos )
| Número de pieza | ICS951403 | |
| Descripción | AMD-K7 System Clock Chip | |
| Fabricantes | ICS | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
ICS951403
AMD-K7TM System Clock Chip
Recommended Application:
ATI chipset with K7 systems
Output Features:
• 3 differential pair open drain CPU clocks (1.5V
external
pull-up; up to 150MHz achieviable through I2C)
• 2 - AGPCLK @ 3.3V
• 8 - PCI @3.3V, including 1 free running
• 1 - 48MHz @ 3.3V
• 1 - 24/48MHz @ 3.3V
• 2- REF @3.3V, 14.318MHz.
Features:
• Programmable ouput frequency
• Programmable ouput rise/fall time
• Programmable group skew
• Real time system reset output
• Spread spectrum for EMI control typically
by 7dB to 8dB,
with programmable spread percentage
• Watchdog timer technology to reset system
if over-clocking causes malfunction
• Uses external 14.318MHz crystal
• Asyncronous CPU and SDRAM clocks
• CPU and PCI outputs are aligned
• CPU - AGP skew <500ps
Pin Configuration
48-Pin SSOP & TSSOP
* Internal 120K pullup resistor on indicated inputs
** Internal 240K pullup resistor on indicated inputs
Block Diagram
PLL2
X1
X2
SEL24_48#
SDATA
SCLK
FS (2:0)
PD#
PCI_STOP#
CPU_STOP#
SPREAD#
XTAL
OSC
PLL1
Spread
Spectrum
Control
Logic
Config.
Reg.
0486B—02/23/04
/2
CPU
DIVDER
Stop
SDRAM
DIVDER
PCI
DIVDER
Stop
AGP
DIVDER
Functionality
48MHz
24_48MHz
REF (1:0)
3 CPUCLKT (2:0)
3 CPUCLKC (2:0)
SDRAM_OUT
PCICLK (6:0)
7
PCICLK_F
AGP (1:0)
2
Bit 7 FS2 FS1 FS0 CPU SDRAM
0 0 0 0 100.00 100.00
0 0 0 1 100.00 133.33
0 0 1 0 100.00 150.00
0 0 1 1 100.00 66.67
0 1 0 0 133.33 133.33
0 1 0 1 125.00 100.00
0 1 1 0 124.00 124.00
0 1 1 1 133.33 100.00
1 0 0 0 112.00 112.00
1 0 0 1 150.00 150.00
1 0 1 0 111.11 166.67
1 0 1 1 110.00 165.00
1 1 0 0 166.67 166.67
1 1 0 1 90.00 90.00
1 1 1 0 48.00 48.00
1 1 1 1 45.00 60.00
AGP SEL = AGP SEL =
PCICLK
0
1
33.33
66.67
50.00
33.33
66.67
50.00
30.00
60.00
50.00
33.33
66.67
50.00
33.33
31.25
31.00
33.33
66.67
62.50
62.00
66.67
50.00
50.00
46.50
50.00
33.60
67.20
56.00
30.00
60.00
50.00
33.33
66.67
55.56
33.00
66.00
55.00
33.33
66.67
55.56
30.00
60.00
45.00
32.00
64.00
48.00
30.00
60.00
45.00
Power Groups
VDD48, GND48 = 48MHz, PLL2
VDDREF, GNDREF= REF, X1, X2
VDD, GND = PLL Core
1 page  
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ICS951403
Byte 15: CPU_SDRAM Skew Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
Description
1
SDRAM (pdel canned)
0
0 Reserved
1
1
1
CPUC0 & T0 (pdel canned)
1
0
CPUC 1:2 & T 1:2 (pdel canned)
Byte 17: Slew Rate Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
1
0
1
0
1
0
1
0
Description
PCI (3:0) Slew Control
PCI_F Slew Control
CPUCLKC0 Slew Control
CPUCLKT0 Slew Control
Byte 19: Slew Rate Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
1
0
1
0
1
0
1
0
Description
48MHz Slew Control
24, 48MHz Slew Control
REF0 Slew Control
REF1 Slew Control
SDRAM Slew Control
Notes:
1. PWD = Power on Default
Byte 16: Slew Rate Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
-
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Description
Byte 18: Slew Rate Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
1
0
1
0
1
0
1
0
Description
PCI (4:7) Slew Control
AGP1 Slew Control
AGP0 Slew Control
Reserved
Byte 20: Slew Rate Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
1
0
1
0
1
0
1
0
Description
CPUCLKC1 Slew Control
CPUCLKT1 Slew Control
CPUCLKC2 Slew Control
CPUCLKT2 Slew Control
0486B—02/23/04
5
5 Page 
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ICS951403
General I2C serial interface information for the ICS951403
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending Byte 0 through Byte 20
(see Note)
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
How to Write:
Controller (Host)
Start Bit
Address D2(H)
Dummy Command Code
Dummy Byte Count
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
ICS (Slave/Receiver)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the read address D3
(H)
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• ICS clock sends Byte 0 through byte 8 (default)
• ICS clock sends Byte 0 through byte X (if X(H) was
written to byte 8).
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
How to Read:
Controller (Host)
Start Bit
Address D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
If 7H has been written to B6
ACK
ICS (Slave/Receiver)
ACK
Byte Count
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
Byte 18
Byte 19
Byte 20
Stop Bit
ACK
ACK
ACK
*See notes on the following page.
0486B—02/23/04
If 12H has been written to B6
ACK
If 13H has been written to B6
ACK
If 14H has been written to B6
ACK
Stop Bit
Byte18
Byte 19
Byte 20
11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet ICS951403.PDF ] | |
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