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Chrontel - (CH7023 / CH7024) TV Encoder

Numéro de référence CH7024
Description (CH7023 / CH7024) TV Encoder
Fabricant Chrontel 
Logo Chrontel 





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CH7024 fiche technique
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Chrontel
CH7023/CH7024
Brief Datasheet
CH7023/CH7024 TV Encoder
Features
TV encoder targeting handheld and similar systems
Support for NTSC, PAL
Video output support for CVBS or S-video
Macrovision7.1.L1 copy protection support for
SDTV (CH7023 only)
Programmable 24-bit/18-bit/16-bit/15-bit/12-bit/8-bit
digital input interface supporting various RGB and
YCrCb (e.g. RGB565, RGB666, RGB888, ITU656
like YCrCb, etc.) input data formats
Support for input resolutions up to 720x480 and
720x576 (e.g. 220x176, 320x240, 640x480, 720x480,
720x576, etc.)
Adjustable brightness, contrast, hue and saturation.
Detect TV / Monitor connection
Two high quality10-bit video DAC outputs
Fully programmable through serial port
Flexible pixel clock frequency from graphics
controller (2.3MHz—64MHz)
Flexible input clock on the crystal or oscillator
(2.3MHz—64MHz)
Flexible up and down scaling on the display
Master and slave mode
Offered in 48-pin LQFP and 49-pin TFBGA Package
IO voltage and SPC/SPD from 1.2V to 3.3V
Programmable power management
Power down current less than 20uA typical
Power consumption of <150mW for one CVBS
output, single terminated and <350mW for two DAC
outputs, double terminated.
General Description
The CH7023/CH7024 is a TV encoder device targeting
handheld, portable video applications such as digital
still cameras and similar portable embedded systems.
The device is able to encode the video signals and
generate synchronization signals for NTSC and PAL
standards.
Supported TV output formats are NTSC-M, NTSC-J,
NTSC-433, PAL-B/D/G/A/I, PAL-M, PAL-N and PAL-
60.
The device accepts different data formats including
RGB and YCrCb (e.g. RGB565, RGB666, RGB888,
ITU656 like YCrCb, etc.) via 24 bit/18 bit/15 bit /12 bit
/8 bit multiplexed digital inputs. Most embedded
controllers are supported. The I/O interface voltage
between CH7023/CH7024 and digital video source
controller can be selected by the I/O supply voltage
(VDDIO). The I/O supply voltage range is from 1.2V to
3.3V. The digital input voltage will follow the I/O
supply voltage.
CH7023/CH7024 is offered in both 48-pin LQFP
package (7 x 7 mm) and 49-pin TFBGA package (6 x 6
mm). CH7023/CH7024 48-pin LQFP package comes
with fixed single serial port address while 49-pin
TFBGA package provide two user selectable serial port
addresses via AS pin pull up or pull down option. Refer
to application note AN-98 for more information.
XIN/FIN,XO
XCLK
P-OUT
2
PLL
H,V
DE
D[23:0]
2
24
Data Demux
CSC
Line Memory
Based Scaler
Sync
Generation
TV Signal
Formatter
Serial Port
Control
DAC 0
DAC 1
Two
10-bit DAC’s
RESET*
SPC
SPD
AS
CVBS
Y
C
ISET
Figure 1: CH7023/CH7024 Block Diagram
209-0000-062 Rev. 1.14, 6/8/2007
1

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