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PDF LTX9863 Data sheet ( Hoja de datos )
| Número de pieza | LTX9863 | |
| Descripción | (LTX9883 / LTX9863) Advanced 10/100 Unmanaged Repeater | |
| Fabricantes | Level One Communications | |
| Logotipo |  |
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Data Sheet - Preliminary Information
LXT9883/LXT9863
MAY 2000
Revision 1.0
Advanced 10/100 Unmanaged Repeater
General Description
The LXT9883 is an advanced, 3.3V, 8-port 10/100
repeater. The LXT9883 is compatible with previous
generations of Level One repeaters from the LXT980 and
LXT918 families. Eight ports directly support 100BASE-
TX/10BASE-T copper media. Two additional Media
Independent Interface (MII) ports (10/100 Mbps
selectable) connect to Media Access Controllers (MACs)
for bridge/switch applications. The LXT9863 offers the
same features and functionality in a six-port device. This
data sheet uses the singular designation “LXT98x3” to
refer to both devices.
The LXT98x3 provides auto-negotiation with parallel
detection for the PHY ports. The LXT98x3 provides two
internal repeater state machines—one operating at
10 Mbps and one at 100 Mbps. Once configured, the
LXT98x3 automatically connects each port to the
appropriate repeater. The LXT98x3 also provides two
Inter-Repeater Backplanes (IRBs) for expansion — one
operating at 10 Mbps and one at 100 Mbps. Up to 240
twisted-pair and MII ports can logically be combined into
one repeater.
Features
• Six or eight 10/100 ports with integrated twisted-pair
PHYs including integrated filters.
• Two 10/100 MIIs for bridging.
• Independent segments for 10 and 100 Mbps
operation.
• Cascadable Inter-Repeater Backplanes (IRBs), with
option for 5V stacking compatibility.
• Integrated LED drivers with user-selectable modes.
• Available in 208-pin QFP package.
• Operating temperature range: 0-70°C, ambient.
LXT98x3 Block Diagram
10M IRB
10 Mbps
Backplane
10BASE-T
Repeater
100M IRB
100 Mbps
Backplane
100BASE-X
Repeater
Port & Mgmt
Status Indicators
Serial LED
Drivers
Refer to www.level1.com for most current information.
10/100 PHY 1
10/100 PHY 2
10/100 PHY 3
10/100 PHY 4
10/100 PHY 5
10/100 PHY 6
10/100 PHY 7
10/100 PHY 8
MII 1
MII 2
TX_I/O
TX_I/O
TX_I/O
TX_I/O
TX_I/O
TX_I/O
TX_I/O
TX_I/O
MII_I/O
MII_I/O
)
1 page  
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LXT9883/LXT9863 Pin Assignments and Signal Descriptions
Table 2: MII #2 Signal Descriptions
Pin Symbol Type1, 2
Description
18 MII2_SPD
205 MII2_RXD0
206 MII2_RXD1
207 MII2_RXD2
208 MII2_RXD3
204 MII2_RXDV
203 MII2_RXCLK
202 MII2_RXER
197 MII2_TXER
196 MII2_TXCLK
195 MII2_TXEN
I Speed Select - MII 2. This signal is sensed at power up, hardware reset, and
PU software reset. Selects operating speed of the respective MII (MAC) interface.
High = 100 Mbps. Low = 10 Mbps.
O Receive Data - MII 2. The LXT98x3 transmits received data to the controller
on these outputs. Data is driven on the falling edge of MII2_RXCLK.
O Receive Data Valid - MII 2. Active High signal, synchronous to
MII2_RXCLK, indicates valid data on MII2_RXD<3:0>.
O Receive Clock - MII 2. MII receive clock for expansion port. This is a 2.5 or
25 MHz clock derived from the CLK25 input (refer to Table 7 on page 14).
O Receive Error - MII 2. Active High signal, synchronous to MII2_RXCLK,
indicates invalid data on MII2_RXD<3:0>.
I Transmit Error - MII 2. MII2_TXER is a 100M-only signal. The MAC
asserts this input when errors occurs in the transmit data stream. The LXT98x3
sends ‘Invalid Code Symbols’ on the line.
O Transmit Clock - MII 2. This is a 2.5 or 25 MHz clock derived from the
CLK25 input (refer to Table 7 on page 14).
I Transmit Enable - MII 2. External controllers drive this input High to indicate
data is transmitted on the MII2_TXD<3:0> pins. Ground this input if unused.
194 MII2_TXD0
193 MII2_TXD1
192 MII2_TXD2
I Transmit Data - MII 2. External controllers use these inputs to transmit data
to the LXT98x3. The LXT98x3 samples MII2_TXD<3:0> on the rising edge
of MII2_TXCLK, when MII2_TXEN is High.
191 MII2_TXD3
188 MII2_COL
O Collision - MII 2. The LXT98x3 drives this signal High to indicate a collision
occurred.
187 MII2_CRS
O Carrier Sense - MII 2. Active High signal indicates LXT98x3 is transmitting
or receiving.
1. I = Input, O = Output, I/O = Input/Output, D = Digital, A = Analog, AI = Analog Input, A I/O = Analog Input/Output, OD = Open Drain,
OS = Open Source, PD = Pull Down, PU = Pull Up.
NC = No Clamp. Pad does not clamp input in the absence of power.
2. Pins are 5V tolerant, unless indicated.
5
5 Page 
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LXT9883/LXT9863 Pin Assignments and Signal Descriptions
Table 5: LED Signal Descriptions
Pin
Symbol
Type1, 2
Description
184 LEDSEL0
185 LEDSEL1
175 LEDABGSEL
183 AUTOBLINK
83 LEDDAT
84 LEDLAT
82 LEDCLK
I3 LED Mode Select - Input. See Note 3 in footer below.
O - OD/OS 00 = Mode 1, 01 = Mode 2, 10 = Mode 3, 11 = Mode 4
These pins are shared with the LEDACT100, LEDCOL10 outputs.
I3 LED Activity Bar Graph Mode Select - Input. See Note 2 in footer
O - OD/OS below.
0 = Base-10 Mode, 1 = Base-2 Mode
Refer to “Activity Graph LEDs” on page 59.
This pin is shared with the Port8_LED2 output.
I3 LED Blink Mode Select - Input. See Note 3 in footer below.
O - OD/OS 0 = Auto blink on, 1 = Auto blink off
This pin is shared with the LEDACT100, LEDCOL10 outputs.
O LED Data. Serial data stream that is shifted into external Serial-to-
Parallel LED drivers. See “Serial LED Interface” on page 20.
O LED Latch. Parallel load clock for external Serial-to-Parallel LED
drivers. See “Serial LED Interface” on page 20.
O LED Clock. Serial data stream clock for external Serial-to-Parallel
LED drivers. See “Serial LED Interface” on page 20.
176 PORT8_LED1
171 PORT7_LED1
167 PORT6_LED1
163 PORT5_LED1
101 PORT4_LED1
97 PORT3_LED1
93 PORT2_LED1
89 PORT1_LED1
O LED Driver 1 - Ports 1 through 8. Programmable LED driver.
OD Active Low. See “Direct Drive LEDs” on page 23.
Port8_LED1 must be pulled High via a 100–500 kΩ resistor if LED
circuit not used.
175 PORT8_LED2
170 PORT7_LED2
166 PORT6_LED2
162 PORT5_LED2
100 PORT4_LED2
96 PORT3_LED2
92 PORT2_LED2
88 PORT1_LED2
O LED Driver 2 - Ports 1 through 8. Programmable LED driver.
OD Active Low. See “Direct Drive LEDs” on page 23.
The Port8_LED2 pin is shared with the LEDABGSEL configuration
input.
1. I = Input, O = Output, I/O = Input/Output, D = Digital, A = Analog, AI = Analog Input, A I/O = Analog Input/Output, OD = Open Drain,
OS = Open Source, PD = Pull Down, PU = Pull Up. Even if the IRB is not used, required pull-up resistors must be installed as listed above.
NC = No Clamp. Pad does not clamp input in the absence of power.
2. Pins are 5V tolerant, unless indicated.
3. Input must be static; Refer to “LED Pins Multiplexed with Configuration Inputs” on page 37 for information on pin use.
11
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| PDF Descargar | [ Datasheet LTX9863.PDF ] | |
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