|
|
PDF ICS952623 Data sheet ( Hoja de datos )
| Número de pieza | ICS952623 | |
| Descripción | Programmable Timing Control Hub | |
| Fabricantes | ICS | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de ICS952623 (archivo pdf) en la parte inferior de esta página. Total 27 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
Integrated
Circuit
Systems, Inc.
ICS952623
Advance Information
Programmable Timing Control Hub™ for Next Gen P4™ processor
Recommended Application:
CK409 clock, Intel Yellow Cover part
Output Features:
• 3 - 0.7V current-mode differential CPU pairs
• 1 - 0.7V current-mode differential SRC pair
• 7 - PCI (33MHz)
• 3 - PCICLK_F, (33MHz) free-running
• 1 - USB, 48MHz
• 1 - DOT, 48MHz
• 2 - REF, 14.318MHz
• 4 - 3V66, 66.66MHz
• 1 - VCH/3V66, selectable 48MHz or 66MHz
Features/Benefits:
• Supports tight ppm accuracy clocks for Serial-ATA
• Supports spread spectrum modulation, 0 to -0.5%
down spread and +/- 0.25% center spread
• Supports CPU clks up to 400MHz in test mode
• Uses external 14.318MHz crystal
• Supports undriven differential CPU, SRC pair in PD#
and CPU_STOP# for power management.
Key Specifications:
Pin Configuration
• CPU/SRC outputs cycle-cycle jitter < 125ps
• 3V66 outputs cycle-cycle jitter < 250ps
• PCI outputs cycle-cycle jitter < 250ps
• CPU outputs skew: < 100ps
• +/- 300ppm frequency accuracy on CPU & SRC clocks
REF0
REF1
VDDREF
X1
X2
1
2
3
4
5
GND 6
Functionality
PCICLK_F0 7
PCICLK_F1 8
CPU SRC 3V66 PCI REF USB/DOT
B6b5 FS_A FS_B MHz MHz MHz MHz MHz MHz
0 0 100 100/200 66.66 33.33 14.318 48.00
0 MID Ref/N0 Ref/N1 Ref/N2 Ref/N3 Ref/N4 Ref/N5
00
1
1 200 100/200 66.66 33.33 14.318 48.00
0 133 100/200 66.66 33.33 14.318 48.00
PCICLK_F2 9
VDDPCI 10
GND 11
PCICLK0 12
PCICLK1 13
1 1 166 100/200 66.66 33.33 14.318 48.00
1 MID Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
0 0 200 100/200 66.66 33.33 14.318 48.00
10
1
1 400 100/200 66.66 33.33 14.318 48.00
0 266 100/200 66.66 33.33 14.318 48.00
1 1 333 100/200 66.66 33.33 14.318 48.00
PCICLK2 14
PCICLK3 15
VDDPCI 16
GND 17
PCICLK4 18
PCICLK5 19
PCICLK6 20
PD# 21
3V66_0 22
3V66_1 23
VDD3V66 24
GND 25
3V66_2 26
3V66_3 27
SCLK 28
56 FS_B
55 VDDA
54 GNDA
53 GND
52 IREF
51 FS_A
50 CPU_STOP#
49 PCI_STOP#
48 VDDCPU
47 CPUCLKT2
46 CPUCLKC2
45 GND
44 CPUCLKT1
43 CPUCLKC1
42 VDDCPU
41 CPUCLKT0
40 CPUCLKC0
39 GND
38 SRCCLKT
37 SRCCLKC
36 VDD
35 Vtt_PWRGD#
34 VDD48
33 GND
32 48MHz_DOT
31 48MHz_USB
30 SDATA
29 3V66_4/VCH
56-pin SSOP & TSSOP
0758—02/08/05
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
1 page  
www.DataSheet4U.com
Integrated
Circuit
Systems, Inc.
ICS952623
Advance Information
Absolute Max
Symbol
Parameter
VDD_A
3.3V Core Supply Voltage
VDD_In 3.3V Logic Input Supply Voltage
Ts
Tambient
Tcase
Storage Temperature
Ambient Operating Temp
Case Temperature
Input ESD protection
ESD prot
human body model
Min
GND - 0.5
-65
0
2000
Max
VDD + 0.5V
VDD + 0.5V
150
70
115
Units
V
V
°C
°C
°C
V
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN TYP
Input High Voltage
Input MID Voltage
Input Low Voltage
Input High Current
Input Low Current
VIH
VMID
VIL
IIH
IIL1
IIL2
3.3 V +/-5%
3.3 V +/-5%
3.3 V +/-5%
VIN = VDD
VIN = 0 V; Inputs with no pull-
up resistors
VIN = 0 V; Inputs with pull-up
resistors
2
1
VSS - 0.3
-5
-5
-200
MAX UNITS NOTES
VDD + 0.3
1.8
V
V
0.8 V
5 uA
uA
uA
Operating Supply Current IDD3.3OP
Full Active, CL = Full load;
350
Powerdown Current
IDD3.3PD
all diff pairs driven
all differential pairs tri-stated
35
12
Input Frequency3
Pin Inductance1
Fi
Lpin
VDD = 3.3 V
14.31818
7
Input Capacitance1
CIN
COUT
Logic Inputs
Output pin capacitance
5
6
CINX
X1 & X2 pins
5
Clk Stabilization1,2
TSTAB
From VDD Power-Up or de-
assertion of PD# to 1st clock
1.8
Modulation Frequency
Triangular Modulation
30
33
Tdrive_SRC
SRC output enable after
PCI_Stop# de-assertion
15
Tdrive_PD#
CPU output enable after
PD# de-assertion
300
Tfall_Pd#
PD# fall time of
5
Trise_Pd#
PD# rise time of
5
Tdrive_CPU_Stop#
CPU output enable after
CPU_Stop# de-assertion
10
Tfall_CPU_Stop#
PD# fall time of
5
Trise_CPU_Stop#
PD# rise time of
5
1Guaranteed by design, not 100% tested in production.
2See timing diagrams for timing requirements.
3 Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet
ppm frequency accuracy on PLL outputs.
0758—02/08/05
mA
mA
mA
MHz
nH
pF
pF
pF
ms
kHz
ns
us
ns
ns
us
ns
ns
3
1
1
1
1
1,2
1
1
1
1
2
1
1
2
5
5 Page 
www.DataSheet4U.com
Integrated
Circuit
Systems, Inc.
ICS952623
Advance Information
I2C Table: Read-Back Register
Byte 0
Bit 7
Bit 6
Pin #
-
-
Bit 5
-
Bit 4
-
Bit 3
-
Name
RESERVED
RESERVED
RESERVED
RESERVED
PCI_STOP#
Bit 2
-
CPU_STOP#
Bit 1
-
FSB
Bit 0
-
FSA
Control Function
RESERVED
RESERVED
RESERVED
RESERVED
PCI STOP# Read
Back
CPU STOP Read
Back
Freq Select 1 Read
Back
Freq Select 0 Read
Back
Type
-
-
-
-
R
R
R
R
01
RESERVED
RESERVED
RESERVED
RESERVED
READBACK
READBACK
READBACK of CPU(2:0)
Frequency
PWD
X
X
X
X
X
X
X
X
I2C Table: Spreading and Device Behavior Control Register
Byte 1
Pin #
Name
Control Function
Bit 7
37,38
SRC/SRC#
SRC Free-Running
Control
Bit 6
37,38
SRC
Output Control
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
46,47
43,44
40,41
46,47
43,44
CPUT2/CPUC2
CPUT1/CPUC1
CPUT0/CPUC0
CPUT2/CPUC2
CPUT1/CPUC1
CPU FREE-RUNNING
CONTROL
Output Control
Output Control
Bit 0
40,41
CPUT0/CPUC0
Output Enable
Type
RW
RW
RW
RW
RW
RW
RW
RW
01
FREE-RUN STOPPABLE
Disable
FREE-RUN
FREE-RUN
FREE-RUN
Disable
Disable
Disable
Enable
STOPPABLE
STOPPABLE
STOPPABLE
Enable
Enable
Enable
PWD
0
1
1
1
1
1
1
1
I2C Table: Output Control Register
Byte 2
Pin #
Name
Control Function
Type
0
1 PWD
Bit 7
37,38
SRC_PD#
Drive Mode
0: Driven in PD# RW Driven
Hi-Z
0
Bit 6
37,38
SRC_Stop#
Drive Mode
0: Driven in
PCI_Stop#
RW Driven
Hi-Z
0
Bit 5
46,47
CPUT2_PD# Drive
Mode
RW Driven
Hi-Z
0
Bit 4
43,44
CPUT1_PD# Drive
Mode
0:driven in PD#
1: Tri-stated
RW Driven
Hi-Z
0
Bit 3
40,41
CPUT0_PD# Drive
Mode
RW Driven
Hi-Z
0
Bit 2
46,47
CPUT2_Stop Drive
Mode
RW Driven
Hi-Z
0
Bit 1
43,44
CPUT1_Stop Drive 0:driven when stopped
Mode
1: Tri-stated
RW
Driven
Hi-Z
0
Bit 0
40,41
CPUT0_Stop Drive
Mode
RW Driven
Hi-Z
0
0758—02/08/05
11
11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet ICS952623.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| ICS952621 | Programmable Timing Control Hub for Next Gen P4 processor |  Integrated Circuit Systems |
| ICS952621 | Programmable Timing Control Hub | ICS |
| ICS952623 | Programmable Timing Control Hub | ICS |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |