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PDF NTD18N06L Data sheet ( Hoja de datos )
| Número de pieza | NTD18N06L | |
| Descripción | Power MOSFET ( Transistor ) | |
| Fabricantes | ON Semiconductor | |
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NTD18N06L, NTDV18N06L
Power MOSFET
18 A, 60 V, Logic Level N−Channel DPAK
Designed for low voltage, high speed switching applications in
power supplies, converters and power motor controls and bridge
circuits.
Features
• AEC Q101 Qualified − NTDV18N06L
• These Devices are Pb−Free and are RoHS Compliant
Typical Applications
• Power Supplies
• Converters
• Power Motor Controls
• Bridge Circuits
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol Value Unit
Drain−to−Source Voltage
Drain−to−Gate Voltage (RGS = 10 MW)
Gate−to−Source Voltage
− Continuous
− Non−repetitive (tpv10 ms)
Drain Current
− Continuous @ TA = 25°C
− Continuous @ TA = 100°C
− Single Pulse (tpv10 ms)
Total Power Dissipation @ TA = 25°C
Derate above 25°C
Total Power Dissipation @ TA = 25°C (Note 2)
Operating and Storage Temperature Range
VDSS
VDGR
VGS
VGS
ID
ID
IDM
PD
TJ, Tstg
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 50 Vdc, VGS = 5.0 Vdc,
L = 1.0 mH, IL(pk) = 12 A, VDS = 60 Vdc)
Thermal Resistance
− Junction−to−Case
− Junction−to−Ambient (Note 1)
− Junction−to−Ambient (Note 2)
EAS
RqJC
RqJA
RqJA
60 Vdc
60 Vdc
Vdc
±15
±20
18
10
54
55
0.36
2.1
−55 to
+175
72
Adc
Apk
W
W/°C
W
°C
mJ
°C/W
2.73
100
71.4
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
TL 260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. When surface mounted to an FR−4 board using the minimum recommended
pad size.
2. When surface mounted to an FR−4 board using the 0.5 sq in drain pad size.
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V(BR)DSS
60 V
RDS(on) TYP
54 mW@5.0 V
ID MAX
18 A
(Note 1)
D
N−Channel
G
S
4
12
3
DPAK
CASE 369C
STYLE 2
MARKING DIAGRAM
& PIN ASSIGNMENT
4
Drain
1
Gate
2
Drain
3
Source
A = Assembly Location*
18N6L = Device Code
Y = Year
WW = Work Week
G = Pb−Free Device
* The Assembly Location code (A) is front side
optional. In cases where the Assembly Location is
stamped in the package, the front side assembly
code may be blank.
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
© Semiconductor Components Industries, LLC, 2014
September, 2014 − Rev. 7
1
Publication Order Number:
NTD18N06L/D
1 page  
NTD18N06L, NTDV18N06L
8 1000
6
Q1
4
QT
Q2
VGS
2
ID = 18 A
TJ = 25°C
0
0 2 4 6 8 10 12
QG, TOTAL GATE CHARGE (nC)
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
100
10
1
1
tr
tf
td(off)
td(on)
VDS = 30 V
ID = 18 A
VGS = 5 V
10
RG, GATE RESISTANCE (W)
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
100
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
20
VGS = 0 V
16 TJ = 25°C
12
8
4
0
0.6 0.68 0.76 0.84 0.92
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
1
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance −
General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the
transition time (tr,tf) do not exceed 10 ms. In addition the total
power averaged over a complete switching cycle must not
exceed (TJ(MAX) − TC)/(RqJC).
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry custom.
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
currents below rated continuous ID can safely be assumed to
equal the values indicated.
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