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PDF MX98725 Data sheet ( Hoja de datos )
| Número de pieza | MX98725 | |
| Descripción | SINGLE CHIP FAST ETHERNET NIC CONTROLLER | |
| Fabricantes | Macronix International | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MX98725 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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www.DataSheet4U.com
PRELIMINARY
MX98725
SINGLE CHIP FAST ETHERNET NIC CONTROLLER
1. FEATURES
• A single chip solution integrates 100/10 Base-T fast
Ethernet MAC, PHY and PMD
• Fully comply to IEEE 802.3u specification
• Operates over 100 meters of STP and category 5
UTP cable
• Support full and half duplex operation in both 100
Base-TX and 10 Base-T mode
• Fully comply to PCI spec. 2.1 with bus clock ranges
from 16MHz to 33MHz
• Fully comply to Advanced Configuration and Power
Interface (ACPI) Rev 1.0
• Fully comply to PCI Bus Power Management Inter-
face spec. Rev 1.0
• Magic Packet TM mode to support Remote-Power
On and Remote-Wake-Up.
• 100/10 Base-T NWAY auto negotiation function
• Large on chip FIFOs for both transmit and receive
operations without external local memory
• Bus master architecture with linked host buffers
delivers the most optimized performance
• 32-bit bus master DMA channel provides ultra low
CPU utilization
• Proprietary Adaptive Network Throughput Control
(ANTC) technology to optimize data integrity and
throughput
• Support up to 256K bytes boot ROM and FLASH
interface
• Three levels of loopback diagnostic capability
• Support a variety of flexible address filtering modes
with 16 CAM address and 512 bits hash
• MicroWire interface to EEPROM for customer's IDs
and configuration data
• Single +5.0V power supply, standard CMOS tech-
nology, 160 pin PQFP package
( Magic Packet technology is a trademark of Advanced
Micro Device Corp.)
2. GENERAL DESCRIPTIONS
The MX98725, second generation of 100/10 Base-T
single chip MAC controller, is designed specifically to
meet future demand on Fast Ethernet networking sys-
tem. Different from MX98715/715a3, MX98725 addition-
ally supports ACPI, Remote-Wake-Up, Remote-Power-
On, and up to 256K Bytes Flash interface to enhance
product's added-on value.
The MX9725 controller is an IEEE802.3u compliant
single chip 32-bit full duplex, 10/100Mbps highly inte-
grated Fast Ethernet combo solution, designed to ad-
dress high performance local area networking (LAN)
system application requirements.
The bus master architecture delivers the performance
needed for today high speed and powerful processors
technology. In other words, the MX98725 not only keeps
CPU utilization low while maximizing data throughput,
but it also optimizes the PCI bandwidth providing the
highest PCI bandwidth utilization. To further reduce
ownership costs the MX98725 uses drivers that are
backward-compatible with the original MXIC MX98713
series controllers.
The MX98725 contains a PCI local bus glueless inter-
face, a Direct Memory Access (DMA) buffer manage-
ment unit, an IEEE802.3u-compliant Media Access Con-
troller (MAC), large Transmit and Receive FIFOs, and
an on-chip 10 Base-T and 100 Base-TX transceiver sim-
plifying system design and improving high speed signal
quality. Full-duplex operation are supported in both 10
Base-T and 100 Base-TX modes that increases the
controller's operating bandwidth up to 200Mbps.
Equipped with intelligent IEEE802.3u-compliant auto-
negotiation, the MX98725-based adapter allows a single
RJ-45 connector to link with the other IEEE802.3u-com-
pliant device completely without any need to set con-
figuration.
In MX98725, an innovative and proprietary design
"Adaptive Network Throughput Control" (ANTC) is built-
in to configure itself automatically by MXIC's driver based
on the PCI burst throughput of different PCs. With this
proprietary design, MX98725 can always optimize its
operating bandwidth, network data integrity and through-
put for different PCs.
P/N:PM0488
REV. 1.7, SEP. 15, 1998
1
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www.DataSheet4U.com
MX98725
Pin Name
TXOP
Type
O
TXON
O
CKREF
LED0
I
O
LED1
O
LED2
O
LED3
O
RESERVED I
VDD
I
GND
I
AVDD
I
AGND
I
Pin No.
160 Pin Function and Driver
157 Twisted pair transmit differential output: Support both 10 Base-T and
100 Base-TX transmit differential output
156 Twisted pair transmit differential output: Support both 10 Base-T and
100 Base-TX transmit differential output
141 Reference clock: 25MHz oscillator clock input
133 Programmable LED pin 0:
CSR9.28=1 Set the LED as Link Speed (10/100) LED.
CSR9.28=0 Set the LED as Activity LED.
Default is Activity LED after reset.
134 Programmable LED pin 1:
CSR9.29=1 Set the LED as Link/Activity LED.
CSR9.29=0 Set the LED as Good Link LED.
Default is RX LED after reset.
135 Programmable LED pin 2:
CSR9.30=1 Set the LED as Collision LED.
CSR9.30=0 Set the LED as TX LED.
Default is TX LED after reset.
136 Programmable LED pin 3:
CSR9.31=1 Set the LED as Full/Half Duplex LED.
CSR9.31=0 Set the LED as RX LED.
Default is RX LED after reset.
10 Reserved pin.
25,26,28,29, Digital Power pins.
30,46,47,61,
71,72,88,89,
95,96,126,127
22,30,31,34, Digital Ground pins.
35,39,40,43,
50,55,56,67,
68,76,77,81,
84,85,92,97,
98,128,129
3,6,8,137,
Analog Power pins.
140,144,147,
148,151,152,
155
4,5,7,9,138, Analog Ground pins.
142,143,145,
146,153,154,
158,159
P/N:PM0488
REV. 1.7, SEP. 15, 1998
5
5 Page 
www.DataSheet4U.com
MX98725
bit 1-0 : Power_State, read/write.
bit7-2 : all 0. Reserved.
bit8 : PME_EN, set 1 to enable PMEB. Set 0 to disable PMEB assertion.
bit 12-9 : Data_Select for report in the Data register located at bit 31:24.
bit 14-13 : Data_Scale, read only.
bit 15 : PME_Status independent of the state of PME_EN.
When set, indicates a assertion of PMEB pin. (support D3 cold).
Write 1 to clear the PMEB signal. Write 0, no effect.
bit 21-16 : Reserved.
bit 22 : B2_B3#, B2_B3 support for D3 hot, meaningful only if BPCC_EN = 1, read only.
bit 23 : BPCC_EN, Bus Power/Clock Control Enable, read only.
bit 31-24 : Data, read only.
5.2 HOST INTERFACE REGISTERS
MX98725 CSRs are located in the host I/O or memory address space. The CSRs are double word aligned and 32
bits long. Definitions and address for all CSRs are as follows :
CSR Mapping
Register
CSR0
CSR1
CSR2
CSR3
CSR4
CSR5
CSR6
CSR7
CSR8
CSR9
CSR10
CSR11
CSR12
CSR13
CSR14
CSR15
CSR16
CSR20
Meaning
Bus mode
Transmit poll demand
Receive poll demand
Receive list demand
Transmit list base address
Interrupt status
Operation mode
Interrupt enable
Missed frame counter
Serial ROM and MII management
Reserved
General Purpose timer
10 Base-T status port
SIA Reset Register
10 Base-T control port
Watchdog timer
Magic Packet Register
NWay Status Register
Offset from CSR Base
Address ( PBIO and PBMA )
00h
08h
10h
18h
20h
28h
30h
38h
40h
48h
50h
58h
60h
68h
70h
78h
80h
A0h
P/N:PM0488
REV. 1.7, SEP. 15, 1998
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MX98725.PDF ] | |
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