|
|
PDF MX98704 Data sheet ( Hoja de datos )
| Número de pieza | MX98704 | |
| Descripción | 100BASE-TX PHYSICAL DATA TRANSCEIVER | |
| Fabricantes | Macronix International | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de MX98704 (archivo pdf) en la parte inferior de esta página. Total 15 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
1.0 FEATURES
INDEX
PRELIMINARY
MX98704
100BASE-TX
PHYSICAL DATA TRANSCEIVER
• Full-Duplex Operation
• Generates 125-Mhz Transmit Clock and 25-Mhz SYMCLK
• Converts 5-Bit Parallel Transmit Data to 1-Bit Serial Data
• Converts Transmit NRZ Data to NRZI Data
• Loopback and Transmitter-Off Modes
• Recovers 125-MHz Clock from Incoming serial NRZI Data Stream
• Reclocks Incoming Serial NRZI Data Stream Using Recovered Clock
• Converts Received Serial Bit Stream to 5-Bit Paralled Form
• Converts NRZI data to NRZ
• Generates 25-MHz Receive Clock
• Package type
-52 PLCC
-52 PQFP
2.0 GENERAL DESCRIPTION
The 100Base-Tx Physical Data Transceiver (PDTR) includes the Physical Data Transmitter (PDT) and the Physical Data
Receiver (PDR). The PDT converts encoded symbols into a serial NRZI data stream. The on-chip PLL generates a bit
rate clock from the TCLKIN or crystal reference. The PDR uses a built-in clock recovery PLL to extract clock information
from the received data stream. The recovered clock is used for serial-to-parallel data conversion.
2.1 FUNCTIONAL BLOCK DIAGRAM
P/N : PM0351
TDAT4-0
SYMCLK
XTAL1,
XTAL2
TCLKIN
RDAT4-0
Input
Register
Shifter
NRZ/
NRZI
25 Mhz
Crystal
Oscillator
Output
Register
Clock Multiplier (PLL)
NRZ/
NRZI
Shifter
Output
Control
Media
Interface
RSCLK
TEST
LPBKB
Divided by 5
Clock & Data
Recovery
(PLL)
Clock
Generator
Control Logic MUX
Normal Mode
Test & Loopback
Signal
Detect
Data Transceiver Functions Block Diagram
1
TDH, TDL
TXEN
RDH, RDL
SDO
SDI
REV. 1.4, SEP. 15, 1997
1 page  
www.DataSheet4U.com
INDEX
MX98704
PIN (PLCC) PIN (PQFP) PIN NAME TYPE
25 18 Test O
26
19
GND
I
27
20
VDD
I
28
21
GND
I
29
22
VDD
I
30
23
GND
I
31
24
OP3
O
32 25 SYMCLK O
33
26
TXEN
I
34
35-39
40
27
28-32
33
TCLKIN
TDAT4-0
I
I
TSB I
41-45
34-38
RDAT4-0 O
46
39
SDO
O
47
40
RSCLK
O
48
41
LPBKB
I
49
42
TEST
I
50
43
VDD
I
51
44
GND
I
52
45
VDD
I
DESCRIPTION
Transmit Filter.
Ground.
Power Supply. 5V
Ground.
Power Supply. 5V
Ground.
Parameter Option (GND is recommended)
Local Symbol Clock. This pin supplies the frequency reference
to the transmit logic. It is the buffered 25MHz oscillator output.
Transmit Enable. When held LOW, the TDH output is forced
LOW, and TDL output is forced HIGH so that the transmitter will
output logical 0. This TTL-level signal has an internal pullup
resistor.
Transmit Clock In. This pin is a 25Mhz optional clock input.
Transmit Data. These five inputs are 4B/5B encoded transmit
data symbols, latched by the rising edge of SYMCLK. TDAT4
is the Most Significant Bit.
Three-State. While this pin input is low, the interface output pins
are forced into the high-impedance state. Pins controlled by this
signal are PDAT4-0, SDO, BYTCLK, SYMCLK and RSCLK.
This TTL-level signal has an internal pullup resistor.
Receive Data. These 5-bit parallel data symbols from trans-
ceiver are clocked by the falling edge of RSCLK and carry the
NRZ data symbols to the controller. RDAT4 is the Most
Significant Bit.
Signal Detect Output. SDO is the SDI input Asynchronized by
RSCLK. It has the same logical sense as SDI.
Recovered Symbol Clock. This is a 25MHz clock, which is
derived from the receive clock synchronization PLL circuit. It is
synchronous to the received serial data, and is the recovered bit
clock divided-by-five.
Loopback. (Active LOW) The function is used during system
loopback test to bypass the transmission medium. This TTL-
level signal has an internal pullup resistor.
Test Mode Enable. When asserted, the PDTR is in Test mode.
For normal operation, TEST pin must be tied High. This TTL-
level signal has an internal pullup resistor.
Power Supply. 5V
Ground.
Power Supply. 5V
5
5 Page 
www.DataSheet4U.com
7.5 ECL TIMING PARAMETERS
NUM
14
15
PARAMETER
ECL Rise Time
ECL Fall Time
7.5.1 ECL TIMING
4.0V
3.3V
14
15
8.0 ORDER INFORMATION
PARTS NO.
MX98704QC
MX98704EC
PACKAGE
52-PIN PLCC
52-PIN PQFP
INDEX
MX98704
MIN
MAX
UNIT
0.9 3.0 ns
0.9 3.0 ns
11
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet MX98704.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| MX98704 | 100BASE-TX PHYSICAL DATA TRANSCEIVER | Macronix International |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |