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PDF M59PW064 Data sheet ( Hoja de datos )
| Número de pieza | M59PW064 | |
| Descripción | 3V Supply LightFlash Memory | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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M59PW064
64 Mbit (4Mb x16, Uniform Block)
3V Supply LightFlash™ Memory
FEATURES SUMMARY
■ MASK-ROM PIN-OUT COMPATIBLE
■ SUPPLY VOLTAGE
– VCC= 2.7 to 3.6V for Read
– VPP = 11.4 to 12.6V for Program
■ ACCESS TIME
– 90ns at VCC = 3.0 to 3.6V
– 100, 110ns at VCC = 2.7 to 3.6V
■ PROGRAMMING TIME
– 9µs per Word typical
– Multiple Word Programming Option
(8s typical Chip Program)
■ SUITABLE FOR ON-BOARD
PROGRAMMING
■ ERASE TIME
– 41s typical Chip Erase
■ UNIFORM BLOCKS
– 32 blocks of 2 Mbits
■ PROGRAM/ERASE CONTROLLER
– Embedded Word Program algorithms
■ 10,000 PROGRAM/ERASE CYCLES per
BLOCK
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
– Device Code : 88AAh
Figure 1. Packages
SO44 (M)
TSOP48 (N)
12 x 20mm
March 2005
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1 page  
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Figure 3. SO Connections
Figure 4. TSOP Connections
M59PW064
A21
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
E
VSS
G
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
1 44
2 43
3 42
4 41
5 40
6 39
7 38
8 37
9 36
10 35
11 M59PW064 34
12 33
13 32
14 31
15 30
16 29
17 28
18 27
19 26
20 25
21 24
22 23
A20
A19
A8
A9
A10
A11
A12
A13
A14
A15
A16
VPP
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
AI07231
VPP
A16
A15
A14
A13
A12
A11
A10
A9
A8
A19
A21
A20
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
E
1 48
12 M59PW064 37
13 36
24 25
VSS
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
VCC
NC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
VSS
VSS
AI07268
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M59PW064
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the Chip Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read Mode.
Table 4. Standard Commands
Bus Write Operations
Command
1st 2nd 3rd 4th 5th 6th
Add Data Add Data Add Data Add Data Add Data Add Data
Read/Reset
1X
F0
3 555 AA 2AA 55 X F0
Auto Select
3 555 AA 2AA 55 555 90
Word Program 4 555 AA 2AA 55 555 A0 PA PD
Block Erase
6 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30
Chip Erase
6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal. The
Command Interface only uses A0-A10 and DQ0-DQ7 to verify the commands; A11-A21, DQ8-DQ15 are Don’t Care.
Table 5. Multiple Word Program Command
Bus Write Operations
Phase
1st 2nd 3rd 4th 5th
nth Final
Add Data Add Data Add Data Add Data Add Data
Add Data Add Data
Set-Up 3 555 AA 2AA 55 555 20
Program n+1 SA PD1 CA PD2 CA PD3 CA PD4 CA PD5
CA PAn FA X
Verify n+1 SA PD1 CA PD2 CA PD3 CA PD4 CA PD5
CA PAn FA X
Note: A Bus Read must be done between each Write cycle where the data is programmed or verified, to Read the Status Register and check
that the memory is ready to accept the next data. SA is the Start Address. CA is the Continue Address. FA is the Final Address. X Don’t
Care, n = number of Words to be programmed.
Table 6. Program, Erase Times and Program, Erase Endurance Cycles
Parameter
Min
Typ (1)
Typical after
10k W/E Cycles (1)
Chip Erase
41 44
Block Erase (128 KWords)
1.5
Program (Word)
9
Chip Program (Multiple Word)
8
Chip Program (Word by Word)
36
Program/Erase Cycles (per Block)
10,000
Note: 1. TA = 25°C, VPP = 12V.
Max
120
6
200
144
144
Unit
s
s
µs
s
s
cycles
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