|
|
PDF UDA1344TS Data sheet ( Hoja de datos )
| Número de pieza | UDA1344TS | |
| Descripción | Low-voltage low-power stereo audio CODEC | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de UDA1344TS (archivo pdf) en la parte inferior de esta página. Total 28 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
INTEGRATED CIRCUITS
DATA SHEET
UDA1344TS
Low-voltage low-power stereo
audio CODEC with DSP features
Preliminary specification
Supersedes data of 2000 Jan 27
File under Integrated Circuits, IC01
2000 Feb 04
1 page  
www.DataSheet4U.com
Philips Semiconductors
Low-voltage low-power stereo audio
CODEC with DSP features
Preliminary specification
UDA1344TS
PINNING
SYMBOL PIN
DESCRIPTION
VSSA(ADC)
VDDA(ADC)
VINL
1 ADC analog ground
2 ADC analog supply voltage
3 ADC input left
Vref(A)
VINR
4 ADC reference voltage
5 ADC input right
VADCN
VADCP
MC1
6 ADC negative reference voltage
7 ADC positive reference voltage
8 mode control 1 input (pull-down)
MP1
9 multi purpose pin 1 output
VDDD
VSSD
SYSCLK
MP2
10 digital supply voltage
11 digital ground
12 system clock input:
256fs, 384fs or 512fs
13 multi purpose pin 2 input
MP3
14 multi purpose pin 3 input
MP4
15 multi purpose pin 4 input
BCK
16 bit clock input
WS 17 word select input
DATAO
18 data output
DATAI
19 data input
MP5
20 multi purpose pin 5 output
(pull-down)
MC2
21 mode control 2 input (pull-down)
VSSA(DAC)
VDDA(DAC)
VOUTR
22 DAC analog ground
23 DAC analog supply voltage
24 DAC output right
VDDO
VOUTL
25 operational amplifier supply voltage
26 DAC output left
VSSO
Vref(D)
27 operational amplifier ground
28 DAC reference voltage
handbook, halfpage
VSSA(ADC) 1
VDDA(ADC) 2
VINL 3
28 Vref(D)
27 VSSO
26 VOUTL
Vref(A) 4
VINR 5
25 VDDO
24 VOUTR
VADCN 6
23 VDDA(DAC)
VADCP 7
22 VSSA(DAC)
UDA1344TS
MC1 8
21 MC2
MP1 9
20 MP5
VDDD 10
VSSD 11
SYSCLK 12
19 DATAI
18 DATAO
17 WS
MP2 13
16 BCK
MP3 14
15 MP4
MGL442
Fig.2 Pin configuration.
2000 Feb 04
5
5 Page 
www.DataSheet4U.com
Philips Semiconductors
Low-voltage low-power stereo audio
CODEC with DSP features
Preliminary specification
UDA1344TS
L3 INTERFACE
The UDA1344TS has a microcontroller input mode. In the
microcontroller control mode, all the digital sound
processing features and the system controlling features
can be controlled by the microcontroller. The controllable
features are:
• System clock frequency
• Data input format
• Power control
• DC filtering
• De-emphasis
• Volume
• Flat/min./max. switch
• Bass boost
• Treble
• Mute.
The exchange of data and control information between the
microcontroller and the UDA1344TS is accomplished
through a serial hardware interface comprising the
following lines:
L3DATA: microcontroller interface data line
L3MODE: microcontroller interface mode line
L3CLOCK: microcontroller interface clock line.
Information transfer via the microcontroller bus is LSB first
and is organized in accordance with the so called
‘L3’ format, in which two different modes of operation can
be distinguished: address mode and data transfer mode.
The address mode is required to select a device
communicating via the L3 interface and to define the
destination registers for the data transfer mode. Data
transfer for the UDA1344TS can only be in one direction:
input to the UDA1344TS to program its sound processing
and other functional features.
Address mode
The address mode is used to select a device for
subsequent data transfer and to define the destination
registers. The address mode is characterized by L3MODE
being LOW and a burst of 8 pulses on L3CLOCK,
accompanied by 8 data bits.
The fundamental timing is shown in Fig.4.
Data bits 7 to 2 represent a 6-bit device address, with bit 7
being the MSB and bit 2 the LSB. The address of the
UDA1344TS is 000101 (bits 7 to 2).
Data bits 1 and 0 indicate the type of subsequent data
transfer as given in Table 13.
Table 13 Selection of data transfer
BIT 1
0
0
1
1
BIT 0
0
1
0
1
TRANSFER
data (volume, bass boost, treble,
de-emphasis, mute, mode and
power control)
not used
status (system clock frequency,
data input/output format and
DC filter)
not used
In the event that the UDA1344TS receives a different
address, it will deselect its microcontroller interface logic.
Data transfer mode
The selection preformed in the address mode remains
active during subsequent data transfers, until the
UDA1344TS receives a new address command.
The fundamental timing of data transfers is essentially the
same as in the address mode and is shown in Fig.5.
The maximum input clock and data rate is 64fs.
All transfers are byte wise, i.e. they are based on groups
of 8 bits. Data will be stored in the UDA1344TS after the
eighth bit of a byte has been received.
A multibyte data transfer is illustrated in Fig.6.
Programming the sound processing and other
features
The sound processing and other feature values are stored
in independent registers.
The first selection of the registers is achieved by the choice
of data type that is transferred. This is performed in the
address mode by bit 1 and bit 0 (see Table 13).
The second selection is performed by the 2 MSBs of the
data byte (bit 7 and bit 6).
The other bits in the data byte (bits 5 to 0) is the value that
is placed in the selected registers.
2000 Feb 04
11
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet UDA1344TS.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| UDA1344TS | Low-voltage low-power stereo audio CODEC | NXP Semiconductors |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |