M58LT128HSB Datasheet PDF - STMicroelectronics
| Part Number | M58LT128HSB | |
| Description | (M58LT128HSB / M58LT128HST) Flash memories | |
| Manufacturers | STMicroelectronics | |
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M58LT128HST
M58LT128HSB
128-Mbit (8 Mb ×16, Multiple Bank, Multilevel interface, Burst)
1.8 V supply, Secure Flash memories
Features
■ Supply voltage
– VDD = 1.7 V to 2.0 V for program, erase
and read
– VDDQ = 2.7 V to 3.6 V for I/O buffers
– VPP = 9 V for fast program
■ Synchronous / Asynchronous Read
– Synchronous Burst Read mode: 52 MHz
– Asynchronous Page Read mode
– Random Access: 85 ns
■ Synchronous Burst Read Suspend
■ Programming time
– 2.5 µs typical Word program time using
Buffer Enhanced Factory Program
command
■ Memory organization
– Multiple Bank memory array: 8-Mbit Banks
– Parameter Blocks (top or bottom location)
■ Dual operations
– program/erase in one Bank while read in
others
– No delay between read and write
operations
■ Block protection
– All blocks protected at power-up
– Any combination of blocks can be protected
with zero latency
– Absolute Write Protection with VPP = VSS
■ Security
– Software security features
– 64-bit unique device number
– 2112-bit user programmable OTP Cells
■ Common Flash Interface (CFI)
■ 100 000 program/erase cycles per block
BGA
TBGA64 (ZA)
10 × 13 mm
■ Electronic signature
– Manufacturer code: 20h
– Top device codes:
M58LT128HST: 88D6h
– Bottom device codes
M58LT128HSB: 88D7h
■ TBGA64 package
– ECOPACK® compliant
March 2007
Rev 1
1/110
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M58LT128HST, M58LT128HSB
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
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Table 22.
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Table 24.
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Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
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Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Bank architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Command codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Standard commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Factory commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Electronic signature codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Protection Register locks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Status Register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
X-Latency Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Burst type definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Dual operations allowed in other banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Dual operations allowed in same bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Dual operation limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Program/Erase times and endurance cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
DC characteristics - currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
DC characteristics - voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Asynchronous Read ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Synchronous Read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Write ac characteristics, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Write ac Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Reset and Power-up ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
TBGA64 10 × 13 mm - 8 × 8 active ball array, 1 mm pitch, package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Top boot block addresses, M58LT128HST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Bottom boot block addresses, M58LT128HSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
CFI query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
CFI query system interface information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Primary algorithm-specific extended query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Protection Register information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Burst Read information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Bank and Erase Block region information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Bank and Erase Block region 1 information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Bank and Erase Block Region 2 Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Command Interface states - modify table, next state . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Command Interface states - modify table, next output state . . . . . . . . . . . . . . . . . . . . . . 103
Command interface states - lock table, next state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Command interface states - lock table, next output state . . . . . . . . . . . . . . . . . . . . . . . . 107
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
5/110
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