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PDF UC62LV4096 Data sheet ( Hoja de datos )
| Número de pieza | UC62LV4096 | |
| Descripción | Low Power CMOS SRAM | |
| Fabricantes | ETC | |
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Low Power CMOS SRAM
256K X 16
UC62LV4096
-55/-70
Features:
• Vcc operation voltage : 1.5 V~ 3.6V
• Low power consumption :
35mA (Max.) operating current
2uA (Typ.) CMOS standby current
• High Speed Access time :
70ns (Max.) at Vcc = 1.5V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Data retention supply voltage as low as 1.2V
• Easy expansion with CE\ and OE\ options
Description
The UC62LV4096 is a high performance, low power
CMOS Static Random Access Memory organized as 262,144
words by 16 and operates from 1.5 V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide
both high speed and low power features with a typical CMOS
standby current of 2uA and maximum access time of 70ns in
1.5V operation.
Easy memory expansion is provided enable (CE\), and
active LOW output enable (OE\) and three-state output
drivers.
The UC62LV4096 has an automatic power down feature,
reducing the power consumption significantly when chip is
deselected.
The US62LV4096 is available in the JEDEC standard 44
pin TSOP (Type II) and 48 pin mini-BGA.
PRODUCT FAMILY
Product Family
Operating
Tempature
UC62LV4096JC
UC62LV4096KC
UC62LV4096AC
UC62LV4096JI
UC62LV4096KI
UC62LV4096AI
0 ~ 70
-40 ~ 85
Vcc Range
1.5V ~ 3.6V
1.5V ~ 3.6V
Speed
(ns)
Vcc=1.5V(Max.)
55/70
55/70
Power Consumption
STANDBY
Operating
Vcc=3.3V(Typ.) Vcc=3.6V(Max.)
2uA 35mA
2uA 35mA
Package
Type
TSOP-44
BGA-48
DICE
TSOP-44
BGA-48
DICE
PIN CONFIGURATIONS
A4
A3
A2
A1
A0
CE
DQ0
DQ1
DQ2
DQ3
VCC
GND
DQ4
DQ5
DQ6
DQ7
WE
A16
A15
A14
A13
A12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
UC62LV4096JC
UC62LV4096JI
44 A5
43 A6
42 A7
41 OE
40 UB
39 LB
38 DQ15
37 DQ14
36 DQ13
35 DQ12
34 GND
33 VCC
32 DQ11
31 DQ10
30 DQ9
29 DQ8
28 NC
27 A8
26 A9
25 A10
24 A11
23 A17
LB OE A0 A1 A2 NC
DQ8
UB
A3
A4
CE DQ0
DQ9 DQ10
A5
A6
DQ1
DQ2
GND DQ11
NC
A7
DQ3
VCC
VCC DQ12
NC
A16
DQ4
GND
DQ14 DQ13 A14
A15
DQ5
DQ6
DQ15
NC
A12
A13
WE DQ7
NC A8 A9 A10 A11 A17
BLOCK DIAGRAM
CE
WE
OE
UB
LB
ROW
Address
COL
Address
CE
WE
OE
UB
LB
MEMORY ARRAY
256K X 16 Bits
COLUMN DECODER
SENSE AMPLIFIER
&
WRITE DRIVER
X16
I/O BUFFER
DQ0 ~ DQ15
U-Chip Technology Corp. LTD.
Reserves the right to modify document contents without notice.
Preliminary Rev. 1.0
PAGE 1
1 page  
www.DataSheet4U.com
Low Power CMOS SRAM
256K X 16
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
ADDRESS
DOUT
tRC
tOH tAA
UC62LV4096
-55/-70
tOH
READ CYCLE2 (1,3,4)
CE
DOUT
READ CYCLE3 (1,4)
tCLZ(5)
ADDRESS
OE
CE
UB/LB
DOUT
tOLZ
tCLZ(5)
tBE
tCE
tRC
tAA
tOE
tCE
tBA
tCHZ(5)
tOH
tOHZ(1,5)
tCHZ(5)
tBDO
NOTES:
1. WE\ is high in read cycle.
2. Device is continuously selected when CE\ = VIL
3. Address valid prior to or coincident with CE\ transition low.
4. OE\ = VIL.
5. Transition is measured ±500mV from steady state with CL=5pF as shown in Figure 1B. The
parameter is guaranteed but not 100% tested.
6.
U-Chip Technology Corp. LTD.
Reserves the right to modify document contents without notice.
Preliminary Rev. 1.0
PAGE 5
5 Page | ||
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| PDF Descargar | [ Datasheet UC62LV4096.PDF ] | |
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