PDF HD49351BP Data sheet ( Hoja de datos )

Número de pieza	HD49351BP
Descripción	CDS/PGA & 10-bit A/D TG Converter
Fabricantes	Renesas Technology
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No Preview Available ! www.DataSheet4U.com HD49351BP/HBP CDS/PGA & 10-bit A/D TG Converter REJ03F0110-0100Z Rev.1.0 Jul 06, 2004 Description The HD49351BP/HBP is a CMOS IC that provides CDS-PGA analog processing (CDS/PGA) suitable for CCD camera digital signal processing systems together with a 10-bit A/D converter and timing generator in a single chip. HD49351 has deleted the stripe mode, pd_mix mode, and added the 5 – 6 pulse and H_msk2 - 4 as contrasted with HD49335. There are address map and timing generator charts besides this specification. May be contacted to our sales department if examining the details. Functions • Correlated double sampling • PGA • 10-bit ADC • Timing generator • Operates using only the 3 V voltage • Corresponds to switching mode of power consumption and operating frequency 220 mW (Typ), maximum frequency: 36 MHz (HD49351HBP) 150 mW (Typ), maximum frequency: 25 MHz (HD49351BP) • ADC direct input mode • FBGA 65-pin package Features • Suppresses low-frequency noise, which output from CCD by the correlated double sampling. • The S/H response frequency characteristics for the reference level can be adjusted using values of external parts and registers. • High sensitivity is achieved due to the high S/N ratio and a wide dynamic range provided by a PG amplifier. • PGA, pulse timing, standby mode, etc., is achieved via a serial interface. • High precision is provided by a 10-bit-resolution A/D converter. • Difference encoded gray code can be selected as an A/D output code. It is effective in suppression of solarization (wave pattern). It is patented by Renesas. • Timing generator generates the all of pulse which are needed for CCD driving. Rev.1.0, Jul 06, 2004, page 1 of 28 1 page HD49351BP/HBP Block Diagram SUB_SW SUB_PD STROB Timing DLL generator ADC_in CDS_in BLKSH BLKC CDS PGA 10bit ADC BLKFB DC offset compensation circuit Serial interface Bias generator AVss DVss1 to 4 Reset D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Rev.1.0, Jul 06, 2004, page 5 of 28 5 Page HD49351BP/HBP Detailed Timing Specifications Detailed Timing Specifications when CDS_in Input Mode is Used Figure 3 shows the detailed timing specifications when the CDS_in input mode is used, and table 8 shows each timing specification. CDS_in SP1 SP2 ADCLK D0 to D9 Black level Signal level (2) (1) (3) (5) (4) (6) (7) (8) (9) (10) Vth Vth Vth Figure 3 Detailed Timing Chart when CDS_in Input Mode is Used Table 8 Timing Specifications when the CDS_in Input Mode is Used No. (1) (2) (3) (4) (5) (6) (7), (8) (9) (10) Timing Black-level signal fetch time SP1 ‘Hi’ period Signal-level fetch time SP2 ‘Hi’ period SP1 falling to SP2 falling time SP1 falling to ADCLK rising inhibit time ADCLK tWH min./tWL min ADCLK rising to digital output holding time ADCLK rising to digital output delay time Symbol tCDS1 tCDS2 tCDS3 tCDS4 tCDS5 tCDS6 tCDS7, 8 tCHLD9 tCOD10 Min — Typ × 0.8 — Typ × 0.8 Typ × 0.85 — 11 — — Typ (1.5) 1/4fCLK (1.5) 1/4fCLK 1/2fCLK (5) — (7) (16) Max — Typ × 1.2 — Typ × 1.2 Typ × 1.15 — — — — Unit ns ns ns ns ns ns ns ns ns OBP Detailed Timing Specifications Figure 4 shows the OBP detailed timing specifications. The OB period is from the fifth to the twelfth clock cycle after the OB pulse is inputted. The average of the black signal level is taken for eight input cycles during the OB period and it becomes the clamp level (DC standard). OB period *1 CDS_in N N+1 N+5 N+12 OBP OB pulse > 2 clock cycles Note: 1. Shifts ±1 clock cycle depending on the OBP input timing. Figure 4 OBP Detailed Timing Specifications N+13 Rev.1.0, Jul 06, 2004, page 11 of 28 11 Page

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