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PDF FDMS9600S Data sheet ( Hoja de datos )
| Número de pieza | FDMS9600S | |
| Descripción | Dual N-Channel PowerTrench MOSFET | |
| Fabricantes | Fairchild Semiconductor | |
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FDMS9600S
Dual N-Channel PowerTrench® MOSFET
Q1: 30V, 32A, 8.5mΩ Q2: 30V, 30A, 5.5mΩ
June 2007
tm
Features
General Description
Q1: N-Channel
Max rDS(on) = 8.5mΩ at VGS = 10V, ID = 12A
Max rDS(on) = 12.4mΩ at VGS = 4.5V, ID = 10A
Q2: N-Channel
Max rDS(on) = 5.5mΩ at VGS = 10V, ID = 16A
Max rDS(on) = 7.0mΩ at VGS = 4.5V, ID = 14A
Low Qg high side MOSFET
Low rDS(on) low side MOSFET
Thermally efficient dual Power 56 package
This device includes two specialized MOSFETs in a unique dual
Power 56 package. It is designed to provide an optimal
Synchronous Buck power stage in terms of efficiency and PCB
utilization. The low switching loss "High Side" MOSFET is com-
plemented by a Low Conduction Loss "Low Side" SyncFET.
Applications
Synchronous Buck Converter for:
Notebook System Power
General Purpose Point of Load
Pinout optimized for simple PCB design
RoHS Compliant
G1
D1
D1
D1 D1
G2
S2
S2
S1/D2
S2
Power 56
5 Q2
6
7
8
4
3
2
Q1 1
MOSFET Maximum Ratings TA = 25°C unless otherwise noted
Symbol
VDS
VGS
ID
PD
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current
-Continuous (Package limited) TC = 25°C
-Continuous (Silicon limited) TC = 25°C
-Continuous
TA = 25°C
-Pulsed
Power Dissipation for Single Operation
TJ, TSTG
Operating and Storage Junction Temperature Range
Thermal Characteristics
(Note 1a)
(Note 1a)
(Note 1b)
Q1 Q2
30 30
±20 ±20
32 30
55 108
12 16
60 60
2.5
1.0
-55 to +150
Units
V
V
A
W
°C
RθJA
RθJA
RθJC
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Case
Package Marking and Ordering Information
(Note 1a)
(Note 1b)
50
120
3 1.2
°C/W
Device Marking
FDMS9600S
Device
FDMS9600S
Package
Power 56
Reel Size
13”
Tape Width
12mm
Quantity
3000 units
©2007 Fairchild Semiconductor Corporation
FDMS9600S Rev.D
1
www.fairchildsemi.com
1 page  
Typical Characteristics (Q1 N-Channel)TJ = 25°C unless otherwise noted
10
ID = 12A
8
VDD =10V
2000
1000
Ciss
6
VDD = 15V
4
VDD = 20V
2
0
0 5 10 15 20 25
Qg, GATE CHARGE(nC)
Figure 7. Gate Charge Characteristics
Coss
100
f = 1MHz
VGS = 0V
Crss
30
0.1
1 10
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure8. CapacitancevsDrain
to Source Voltage
30
100
10
1ms
1
SINGLE PULSE
TJ = MAX RATE
RθJA = 120oC/W
0.1 TA = 25oC
THIS AREA IS LIMITED
BY rDS(ON)
0.01
0.1
1
10ms
100ms
1s
10s
DC
10 100
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 9. Forward Bias Safe
Operating Area
300
VGS = 10V
100
10
SINGLE PULSE
RθJA = 120oC/W
TA = 25oC
1
0.5
10-3
10-2
10-1
100
101
t, PULSE WIDTH (s)
102
Figure 10. Single Pulse Maximum
Power Dissipation
103
2
1 DUTY CYCLE-DESCENDING ORDER
D = 0.5
0.2
0.1
0.05
0.1 0.02
0.01
PDM
0.01
0.002
10-3
SINGLE PULSE
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
10-2
10-1
100
101
t, RECTANGULAR PULSE DURATION (s)
Figure 11. Transient Thermal Response Curve
102
103
FDMS9600S Rev.D
5 www.fairchildsemi.com
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet FDMS9600S.PDF ] | |
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