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National Semiconductor - UART

Numéro de référence NS16550A
Description UART
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Accessing the NS16550A
UART in the PS 2 Model 50
60 70 and 80
National Semiconductor
Application Note 628
Martin S Michael
July 1989
INTRODUCTION
This paper reviews fundamental concepts of the Micro
Channel Architecture and their relation to the NS16550A
UART All 4 of the PS 2 personal computers reviewed use
the NS16550A for asynchronous serial communication
The first part is an overview of the PS 2 system board and
Micro Channel Architecture (MCA) in the Models 50 60 70
and 80 personal computers The next part explains the ba-
sic configuration and system initialization procedures for the
UART that occur after power-up The last part describes the
overall interrupt procedure and the advantages of using the
on-chip FIFOs of the NS16550A These explanations de-
scribe the CPU accesses to the UART via MCA Timing dia-
grams in the appendix show these accesses to the UART
OVERVIEW OF THE PS 2 MODEL 50 60 70 AND 80
SYSTEM ARCHITECTURE
The block diagram indicates a number of identical functions
that all system boards have (Figure 1) Each system CPU
has an 8 channel DMA Controller and an optional math co-
processor associated with it via the local bus The DMA
Controller emulates the dual 8237 DMA controllers found on
the IBM AT Additionally this DMA Controller provides Ex-
tended and Virtual Mode operation These modes allow it to
interface with various DMA slave devices and the CPU to
dynamically select the arbitration level for 2 of the DMA
channels A central arbitration point allows certain adapter
cards and system peripherals to compete for DMA trans-
fers These adapter cards must have the appropriate arbi-
tration and DMA logic
Buffers condition the bus signals from the system CPU and
send them directly to the Micro Channel Interface These
signals after further buffering reach the system memory
and the system peripherals The system ROM on the Mod-
els 50 and 60 also interfaces via these buffers to the 80286
CPU In the Models 70 and 80 the 128 kbyte ROM interfac-
es via the local bus to the 80386 CPU
The dynamic RAM is expandable on the system board or on
adapter cards DMA controller addressing capability limits
the total DRAM available on any of these systems to 16
Mbytes The maximum DRAM available on the various sys-
tem boards is
1 Model 50 Type 1 e 1 Mbyte Type 2 e 2 Mbytes
2 Model 60 e 1 Mbyte
3 Model 70 Type 1 or Type 2 e 6 Mbytes
4 Model 80 Type 1 e 2 Mbytes Type 2 e 4 Mbytes
Beyond the memory coprocessor and DMA there are a
number of major peripheral functions resident on the system
board These are
1 serial port (NS16550A)
2 video graphics controller
3 diskette controller
4 parallel port
5 keyboard and pointing device controller
6 CMOS clock and configuration RAM
7 dual interrupt controllers (16 channels)
8 timer (3 channels)
The configuration software for the serial port on the system
board restricts the addressing of the NS16550A to COM1
and COM2 on the Models 50 60 70 and 80 Adapter card
serial ports however may be assigned any 1 of the 8 base
I O addresses
Adding adapter cards extends the PS 2 functionality be-
yond the system board These cards plug into the Micro
Channel Bus connectors and conform to the MCA proto-
cols
OVERVIEW OF THE MICRO CHANNEL ARCHITECTURE
MCA functionality increases as the data bus width increases
from 16 to 32 bits Both bus widths support certain funda-
mental features regardless of the data bus width One of
these is a centralized arbitration controller that allows up to
16 devices to contend for the 8 available DMA channels
These devices compete based on an assigned priority level
for the DMA resource A ‘‘fairness’’ option allows lower pri-
ority devices to compete successfully for a DMA channel
even though higher priority devices may require a transfer
If the fairness option is enabled each device that has re-
ceived DMA service must wait until all other devices re-
questing the DMA have been serviced before they are al-
lowed to compete for the DMA resource again MCA fixes
the priority levels of the DMA channels except for channels
0 and 4 which the CPU can program to any priority level
The DMA channels are capable of both 8- and 16-bit trans-
fers
MCA also features level sensitive interrupts provides for
interrupt sharing and brings 11 of the 16 hardware interrupts
out to the Micro Channel Bus for the adapters to use The
last section of this paper describes interrupt handling in
more detail
Previous PC architectures used jumpers and switches to
configure the adapter cards MCA uses programmable con-
figuration registers on each adapter card instead This adds
to system flexibility by allowing automatic card configuration
via software
The Models 50 and 60 support 8- or 16-bit transfers over a
64 kbyte range of I O addresses and over a 16 Mbyte range
of memory addresses The Models 70 and 80 have all of
these capabilities and can execute 32-bit transfers over the
64 kbyte I O address range or the 4 Gbyte memory address
range
IBM PC PS 2 and MicroChannel are registered trademarks of International Business Machines Corporation
C1995 National Semiconductor Corporation TL C 10456
RRD-B30M75 Printed in U S A

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