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Numéro de référence | V58C2512164SBI5 | ||
Description | High Performance 512M-Bit DDR SDRAM | ||
Fabricant | ProMOS Technologies | ||
Logo | |||
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V58C2512(804/404/164)SB
HIGH PERFORMANCE 512 Mbit DDR SDRAM
4 BANKS X 16Mbit X 8 (804)
4 BANKS X 32Mbit X 4 (404)
4 BANKS X 8Mbit X 16 (164)
Clock Cycle Time (tCK2.5)
Clock Cycle Time (tCK3)
System Frequency (fCK max)
5
DDR400
6ns
5ns
200 MHz
6
DDR333
6ns
-
166 MHz
75
DDR266
7.5ns
-
133 MHz
Features
■ High speed data transfer rates with system frequency
up to 200MHz
■ Data Mask for Write Control
■ Four Banks controlled by BA0 & BA1
■ Programmable CAS Latency: 2.5, 3
■ Programmable Wrap Sequence: Sequential
or Interleave
■ Programmable Burst Length:
2, 4, 8 for Sequential Type
2, 4, 8 for Interleave Type
■ Automatic and Controlled Precharge Command
■ Power Down Mode
■ Auto Refresh and Self Refresh
■ Refresh Interval: 8192 cycles/64 ms
■ Available in 60 Ball FBGA AND 66 Pin TSOP II
■ SSTL-2 Compatible I/Os
■ Double Data Rate (DDR)
■ Bidirectional Data Strobe (DQS) for input and output
data, active on both edges
■ On-Chip DLL aligns DQ and DQs transitions with CK
transitions
■ Differential clock inputs CK and CK
■ Power Supply 2.5V ± 0.2V
■ Power Supply 2.6V ± 0.1V for DDR400
■ tRAS lockout supported
■ Concurrent auto precharge option is supported
*Note:
(-5) Supports PC3200 module with 3-3-3 timing
(-6) Supports PC2700 module with 2.5-3-3 timing
(-75) Supports PC2100 module with 2.5-3-3 timing
Description
The V58C2512(804/404/164)SB is a four bank DDR
DRAM organized as 4 banks x 16Mbit x 8 (804), 4 banks x
32Mbit x 4 (404), 4 banks x 8Mbit x 16 (164). The
V58C2512(804/404/164)SB achieves high speed data
transfer rates by employing a chip architecture that
prefetches multiple bits and then synchronizes the output
data to a system clock.
All of the control, address, circuits are synchronized
with the positive edge of an externally supplied clock. I/O
transactions are occurring on both edges of DQS.
Operating the four memory banks in an interleaved
fashion allows random access operation to occur at a
higher rate than is possible with standard DRAMs. A se-
quential and gapless data rate is possible depending on
burst length, CAS latency and speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
Package Outline
JEDEC 66 TSOP II
60 FBGA
•
V58C2512(804/404/164)SB Rev.1.4 March 2007
CK Cycle Time (ns)
-5 -6
••
1
-75
•
Power
Std.
•
L
•
Temperature
Mark
Blank
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Pages | Pages 61 | ||
Télécharger | [ V58C2512164SBI5 ] |
No | Description détaillée | Fabricant |
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