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PDF FT2232D Data sheet ( Hoja de datos )
| Número de pieza | FT2232D | |
| Descripción | Dual USB UART/FIFO I.C. | |
| Fabricantes | Future Technology | |
| Logotipo |  |
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™
Future Technology Devices International Ltd.
FT2232D Dual USB
UART/FIFO I.C.
The FT2232D is an updated version of FTDI’s 3rd generation USB UART / FIFO I.C. family.This device features two
Multi-Purpose UART / FIFO controllers which can be configured individually in several different modes. As well as a
UART interface, FIFO interface and Bit-Bang IO modes of the 2nd generation FT232BM and FT245BM devices, the
FT2232D offers a variety of additional new modes of operation, including a Multi-Protocol Synchronous Serial Engine
interface which is designed specifically for synchronous serial protocols such as JTAG, I2C, and SPI bus.
The FT2232D is fully pin to pin compatible with the previous FT2232C and FT2232L devices. In addition to supporting
all of the FT2232C / FT2232L functionallity, the FT2232D has an additional interface mode, CPU FIFO mode, and is
specified for -40 to +85 degrees C operation.
The FT2232D is available in Pb-free (RoHS compliant) compact 48-Lead LQFP package.
Copyright © Future Technology Devices International Ltd. 2006
1 page  
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FT2232D Dual USB UART / FIFO I.C.
• Programmable Receive Buffer Timeout
• Extended EEPROM Support
The TX buffer timeout is programmable over USB in The FT2232D supports 93C46 (64 x 16 bit), 93C56
1ms increments from 1ms to 255ms, thus allowing
(128 x 16 bit), and 93C66 (256 x 16 bit) EEPROMs.
the device to be better optimised for protocols
The extra space is not used by the device, however
requiring faster response times from short data
it is available for use by other external MCU / logic
packets.
whilst the FT2232D is being held in reset. There is
now an adiitional 64 words of space available (128
• Relaxed VCC Decoupling
bytes total) in the user area when a 93C56 or 93C66
The improved level of Vcc decoupling that was
incorporated into BM devices has also been
is used.
implemented in the FT2232D device.
• USB 2.0 (full speed option)
• Baud Rate Pre-Scaler Divisors
The FT2232D (UART mode) baud rate pre-scaler
supports division by (n+0), (n+0.125), (n+0.25),
(n+0.375), (n+0.5), (n+0.625), (n+0.75) and (n+0.875)
where n is an integer between 2 and 16,384 (214).
An EEPROM based option allows the FT2232D to
return a USB 2.0 device descriptor as opposed to
USB 1.1. Note : The device would be a USB 2.0 Full
Speed device (12Mb/s) as opposed to a USB 2.0
High Speed device (480Mb/s).
DS2232D Version 0.91
© Future Technology Devices International Ltd. 2006 Page of 51
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FT2232D Dual USB UART / FIFO I.C.
5.0 Pin Definitions
This section decribes the operation of the FT2232D pins. Common pins are defined in the first section, then the I/O
pins are defined, by chip mode. More detailed descriptions of the operation of the I/O pins are provided in section 9.
5.1 Common Pins
The operation of the following FT2232D pins stay the same, regardless of the chip mode :-
USB INTERFACE GROUP
Pin# Signal
Type
7
USBDP
I/O
8
USBDM
I/O
Description
USB Data Signal Plus ( Requires 1.5K pull-up to 3V3OUT or RSTOUT# )
USB Data Signal Minus
EEPROM INTERFACE GROUP
Pin# Signal
Type
Description
48 EECS I/O EEPROM – Chip Select. Tri-State during device reset. **Note 1
1 EESK
OUTPUT Clock signal to EEPROM. Tri-State during device reset, else drives out. **Note 1
2
EEDATA
I/O
EEPROM – Data I/O Connect directly to Data-In of the EEPROM and to Data-
Out of the EEPROM via a 2.2K resistor. Also, pull Data-Out of the EEPROM
to VCC via a 10K resistor for correct operation. Tri-State during device reset.
**Note 1
MISCELLANEOUS SIGNAL GROUP
Pin# Signal
Type
Description
4 RESET# INPUT Can be used by an external device to reset the FT2232D. If not required, tie to
VCC. **Note 1
5 RSTOUT# OUTPUT Output of the internal Reset Generator. Drives low for 5.6 ms after VCC > 3.5V
and the internal clock starts up, then clamps it’s output to the 3.3V output of the
internal regulator. Taking RESET# low will also force RSTOUT# to drive low.
RSTOUT# is NOT affected by a USB Bus Reset.
47 TEST
INPUT Puts device into I.C. test mode – must be tied to GND for normal operation.
41 PWREN# OUTPUT Goes Low after the device is configured via USB, then high during USB suspend.
Can be used to control power to external logic using a P-Channel Logic Level
MOSFET switch. Enable the Interface Pull-Down Option in EEPROM when using
the PWREN# pin in this way.
43 XTIN
INPUT
Input to 6MHz Crystal Oscillator Cell. This pin can also be driven by an external
6MHz clock if required. Note : Switching threshold of this pin is VCC/2, so if
driving from an external source, the source must be driving at 5V CMOS level or
a.c. coupled to centre around VCC/2.
44 XTOUT OUTPUT Output from 6MHz Crystal Oscillator Cell. XTOUT stops oscillating during USB
suspend, so take care if using this signal to clock external logic.
**Note 1 - During device reset, these pins are tri-state but pulled up to VCC via internal 200K resistors.
DS2232D Version 0.91
© Future Technology Devices International Ltd. 2006 Page 11 of 51
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet FT2232D.PDF ] | |
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