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PDF 6227CA Data sheet ( Hoja de datos )
| Número de pieza | 6227CA | |
| Descripción | ISL6227CA | |
| Fabricantes | Intersil Corporation | |
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®
Data Sheet
Dual Mobile-Friendly PWM Controller with
DDR Option
The ISL6227 dual PWM controller delivers high efficiency
precision voltage regulation from two synchronous buck DC/DC
converters. It was designed especially to provide power
regulation for DDR memory, chipsets, graphics and other
system electronics in Notebook PCs. The ISL6227’s wide
input voltage range capability allows for voltage conversion
directly from ac/dc adaptor or Li-Ion battery pack.
Automatic mode transition of constant-frequency synchronous
rectification at heavy load, and hysteretic (HYS) diode-
emulation at light load, assure high efficiency over a wide range
of conditions. The HYS mode of operation can be disabled
separately on each PWM converter if constant-frequency
continuous-conduction operation is desired for all load levels.
Efficiency is further enhanced by using the lower MOSFET
rDS(ON) as the current sense element.
Voltage-feed-forward ramp modulation, current mode control,
and internal feedback compensation provide fast response to
input voltage and load transients. Input current ripple is
minimized by channel-to-channel PWM phase shift of 0°, 90°, or
180° (determined by input voltage and status of the DDR pin).
The ISL6227 can control two independent output voltages
adjustable from 0.9V to 5.5V, or by activating the DDR pin,
transform into a complete DDR memory power supply solution.
In DDR mode, CH2 output voltage VTT tracks CH1 output
voltage VDDQ. CH2 output can both source and sink current, an
essential power supply feature for DDR memory. The reference
voltage VREF required by DDR memory is generated as well.
In dual power supply applications the ISL6227 monitors the
output voltage of both CH1 and CH2. An independent PGOOD
(power good) signal is asserted for each channel after the soft-
start sequence has completed, and the output voltage is within
PGOOD window. In DDR mode CH1 generates the only
PGOOD signal.
Built-in overvoltage protection prevents the output from going
above 115% of the set point by holding the lower MOSFET on
and the upper MOSFET off. When the output voltage re-enters
regulation, PGOOD will go HIGH and normal operation
automatically resumes. Once the soft-start sequence has
completed, undervoltage protection latches the offending
channel off if the output drops below 75% of its set point value.
Adjustable overcurrent protection (OCP) monitors the voltage
drop across the rDS(ON) of the lower MOSFET. If more precise
current-sensing is required, an external current sense resistor
may be used.
Applications
• Notebook PCs and Desknotes
• Hand-held portable instruments
• Tablet PCs/Slates
1
ISL6227
March 2004
FN9094.1
Features
• Provides regulated output voltage in the range 0.9V–5.5V
• Operates from an input battery voltage range of 5V to 24V
or from 3.3V/5V system rail
• Complete DDR1 and DDR2 memory power solution with
VTT tracking VDDQ/2 and a VDDQ/2 buffered reference
output
• Flexible PWM or HYS plus PWM mode selection with HYS
diode emulation at light loads for higher system efficiency
• rDS(ON) current sensing
• Excellent dynamic response with voltage feed-forward and
current mode control accommodating wide range LC filter
selections
• Undervoltage lock-out on VCC pin
• Power-good, overcurrent, overvoltage, undervoltage
protection for both channels
• Synchronized 300kHz PWM operation in PWM mode
• Pb-Free Available as an Option
Ordering Information
PART # TEMP. (°C)
PACKAGE
PKG.
DWG. #
ISL6227CA
-10 to 100 28 Ld SSOP
M28.15
ISL6227CAZ
(Note)
-10 to 100 28 Ld SSOP (Pb-Free)
M28.15
ISL6227CA-T -10 to 100 28 Ld SSOP Tape and Reel M28.15
ISL6227CAZ-T -10 to 100 28 Ld SSOP Tape and Reel M28.15
(Note)
(Pb-Free)
NOTE: Intersil Pb-Free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-Free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J Std-020B.
Pinout
ISL6227 (28 LD SSOP) TOP VIEW
GND 1
LGATE1 2
PGND1 3
PHASE1 4
UGATE1 5
BOOT1 6
ISEN1 7
EN1 8
VOUT1 9
VSEN1 10
OCSET1 11
SOFT1 12
DDR 13
VIN 14
28 VCC
27 LGATE2
26 PGND2
25 PHASE2
24 UGATE2
23 BOOT2
22 ISEN2
21 EN2
20 VOUT2
19 VSEN2
18 OCSET2
17 SOFT2
16 PG2/REF
15 PG1
1 page  
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ISL6227
Typical Operation Performance
100
90
80
70
60
50
40
30
20
10
0
0.01
EFF@ 5V
EFF@ 12V
EFF@ 19.5V
EFF@ 5V, PWM
EFF@ 12V, PWM
EFF@ 19.5V, PWM
0.1 1
LOAD CURRENT (A)
10
FIGURE 1. EFFICIENCY OF CHANNEL 1, 2.5V,
HYS/PWM MODE
100
90
80
70
60
50
40
30
20
10
0
0.01
EFF@ 5V
EFF@ 12V
EFF@ 19.5V
EFF@ 5V, PWM
EFF@ 12V, PWM
EFF@ 19.5V, PWM
0.1 1
LOAD CURRENT (A)
10
FIGURE 2. EFFICIENCY OF CHANNEL 2, 1.8V,
HYS/PWM MODE
2.54
2.53
2.52
2.51
Vout @ 5V
Vout @ 12V
Vout @ 19.5V
Vout @ 5V, PWM
Vout @ 12V, PWM
Vout @ 19.5V, PWM
2.5
2.49
2.48
2.47
0
123
LOAD CURRENT (A)
4
5
FIGURE 3. OUTPUT VOLTAGE OF CHANNEL 1 vs LOAD
308
306
304
302
300
298
296
294
292
290
288
286
-20
0
75% Quantile
Frequency Mean
25% Quantile
20 40 60 80
TEMPERATURE (°C)
100 120
FIGURE 5. SWITCHING FREQUENCY OVER TEMPERATURE
5
1.83
1.82
1.81
Vout @ 5V
Vout @ 12V
Vout @ 19.5V
Vout @ 5V, PWM
Vout @ 12V, PWM
Vout @ 19.5V, PWM
1.8
1.79
1.78
0
123 4
LOAD CURRENT (A)
5
FIGURE 4. OUTPUT VOLTAGE OF CHANNEL 2 vs LOAD
0.9025
0.902
0.9015
0.901
0.9005
0.9
0.8995
0.899
0.8985
0.898
0.8975
-20
0
75% Quantile
Vref Mean
25% Quantile
20 40 60 80
TEMPERATURE (°C)
100
FIGURE 6. REFERENCE VOLTAGE ACCURACY OVER
TEMPERATURE
120
5 Page 
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ISL6227
PG2/REF (Pin 16)
This pin has a double function, depending on the mode of
operation.
When the chip is used as a dual channel PWM controller
(DDR = 0), the pin provides an open drain PGOOD2 function
for the second channel the same way as PG1. The pin is
pulled low when the second channel output is out of
-11% -- +15% of the set value.
In DDR mode (DDR=1), this pin is the output of the buffer
amplifier that takes VDDQ/2 voltage applied to OCSET2 pin
from the resister divider. It can source a typical 10mA
current.
OCSET2 (Pin 18)
In a dual channel application with DDR = 0, a resistor from
this pin to ground sets the overcurrent threshold for the
second channel controller. Its voltage is the buffered internal
0.9V reference.
In the DDR application with DDR=1, this pin connects to the
center point of a resistor divider tracking the VDDQ/2. This
voltage is then buffered by an amplifier voltage follower and
sent to the PG2/REF pin. It sets the reference voltage of
channel 2 for its regulation.
VCC (Pin 28)
This pin powers the controller.
Typical Application
Figures 31 and 32 show the application circuits of a dual
channel DC/DC converter for a notebook PC.
The power supply in Figure 31 provides +2.5V and +1.8V
voltages for memory and the graphics interface chipset from
a +5.0-24VDC battery voltage.
Figure 32 illustrates the application circuit for a DDR memory
power solution. The power supply shown in Figure 32
generates +2.5V VDDQ voltage from a battery. The +1.25V
VTT termination voltage tracks VDDQ/2 and is derived from
+2.5V VDDQ. To complete the DDR memory power
requirements, the +1.25V reference voltage is provided
through the PG2 pin.
11
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| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet 6227CA.PDF ] | |
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