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PDF ICS487-25 Data sheet ( Hoja de datos )
| Número de pieza | ICS487-25 | |
| Descripción | Quad PLL | |
| Fabricantes | ICS | |
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ICS487-25
Quad PLL for DTV
Description
The ICS487-25 generates five high-quality,
high-frequency clock outputs. It is designed to replace
crystals and crystal oscillators in DTV applications.
Using ICS’ patented Phase Locked Loop (PLL)
techniques, the device runs from a lower frequency
crystal or clock input.
Because there is zero ppm frequency synthesis error
on the audio clocks, the audio will remain locked to the
video.
Features
• Packaged in 16-pin TSSOP
• Available in Pb-free packaging
• Replaces multiple crystals and oscillators
• Input crystal or clock frequency of 27 MHz
• Zero ppm frequency synthesis error
• Duty cycle of 45/55
• Operating voltage of 3.3 V
• Advanced, low power CMOS process
Block Diagram
2
S1:0
27 MHz
clock or
crystal
input
X1/ICLK
X2
Crystal
Oscillator/
Clock
Buffer
External capacitors
may be required.
VDD
3
PLL1
PLL2
PLL3
ACLK
20M
48M
33.0M
PLL4
24.576M
3
GND
PDTS (all outputs and PLLs)
MDS 487-25 A
1
Revision 050604
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 297-1201 l www.icst.com
1 page  
ICS487-25
Quad PLL for DTV
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature 0 to +70°C
Parameter
Symbol Conditions
Min.
Input Frequency
Output Rise Time
Output Fall Time
Output Clock Duty Cycle
fIN
tOR 20% to 80%, Note 1
tOF 80% to 20%, Note 1
at VDD/2, Note 1
45
Absolute Clock Period Jitter
Note 1
Frequency Synthesis Error
All outputs
Output Enable Time
tOE PDTS high to output
locked to ±1%
Output Disable Time
Audio Clock Stabilization Time
tOD PDTS low to tri-state
Time from a change
in S1 or S0 until
output stable within
±1%
Typ.
27
1.2
1.0
50
±175
0
250
20
50
Note 1: Measured with a 15 pF load.
Thermal Characteristics
Max. Units
MHz
ns
ns
55 %
ps
ppm
µs
ns
µs
Parameter
Symbol Conditions
Thermal Resistance Junction to
Ambient
θJA Still air
θJA 1 m/s air flow
θJA 3 m/s air flow
Thermal Resistance Junction to Case θJC
Marking Diagram
Min.
Typ.
78
70
68
37
Max.
Units
°C/W
°C/W
°C/W
°C/W
16 9
487G-25
######
YYWW$$
18
Notes:
1. ###### is the lot code.
2. YYWW is the last two digits of the year, and the week
number that the part was assembled.
MDS 487-25 A
5
Revision 050604
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 297-1201 l www.icst.com
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet ICS487-25.PDF ] | |
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