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PDF ICS432I-101 Data sheet ( Hoja de datos )
| Número de pieza | ICS432I-101 | |
| Descripción | DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER | |
| Fabricantes | ICS | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
ICS8432I-101
700MHZ,
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
The ICS8432I-101 is a general purpose, dual out- • Dual differential 3.3V LVPECL outputs
ICS
HiPerClockS™
put Differential-to-3.3V LVPECL high frequency
synthesizer and a member of the HiPerClockS™
•
Selectable CLK, nCLK or LVCMOS/LVTTL TEST_CLK
family of High Performance Clock Solutions from • TEST_CLK can accept the following input levels:
ICS. The ICS8432I-101 has a selectable LVCMOS or LVTTL
TEST_CLK or CLK, nCLK inputs.The TEST_CLK input accepts
LVCMOS or LVTTL input levels and translates them to 3.3V • CLK, nCLK pair can accept the following differential
LVPECL levels.The CLK, nCLK pair can accept most standard input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
differential input levels.The VCO operates at a frequency range • CLK, nCLK or TEST_CLK maximum input frequency: 40MHz
of 250MHz to 700MHz. The VCO frequency is programmed in
steps equal to the value of the input differential or single ended • Output frequency range: 25MHz to 700MHz
reference frequency. The VCO and output frequency can be
programmed using the serial or parallel interfaces to the
configuration logic. The low phase noise characteristics of the
ICS8432I-101 makes it an ideal clock source for Gigabit
• VCO range: 250MHz to 700MHz
• Accepts any single-ended input signal on CLK input
with resistor bias on nCLK input
Ethernet and SONET applications.
• Parallel interface for programming counter
and output dividers
• RMS period jitter: 5ps (maximum)
• Cycle-to-cycle jitter: 25ps (maximum)
• 3.3V supply voltage
• -40°C to 85°C ambient operating temperature
• Lead-Free package fully RoHS compliant
BLOCK DIAGRAM
VCO_SEL
CLK_SEL
TEST_CLK
CLK
nCLK
0
1
MR
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M0:M8
N0:N1
PLL
PHASE DETECTOR
VCO
0 ÷1
÷2
÷ M 1 ÷4
÷8
CONFIGURATION
INTERFACE
LOGIC
PIN ASSIGNMENT
FOUT0
nFOUT0
FOUT1
nFOUT1
32 31 30 29 28 27 26 25
M5 1
M6 2
M7 3
M8 4
N0 5
N1 6
nc 7
VEE 8
ICS8432I-101
24 CLK
23 TEST_CLK
22 CLK_SEL
2 1 VCCA
20 S_LOAD
19 S_DATA
18 S_CLOCK
17 MR
9 10 11 12 13 14 15 16
TEST
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
8432DYI-101
www.icst.com/products/hiperclocks.html
1
REV. A MAY 23, 2005
1 page  
Integrated
Circuit
Systems, Inc.
ICS8432I-101
700MHZ,
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
Inputs, V
I
Outputs, IO
Continuous Current
Surge Current
Package Thermal Impedance, θJA
Storage Temperature, T
STG
4.6V
-0.5V to V + 0.5 V
CC
50mA
100mA
47.9°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
VCC
VCCA
VCCO
IEE
ICCA
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
3.465
3.465
120
15
Units
V
V
V
mA
mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions Minimum Typical Maximum
VCO_SEL, CLK_SEL, MR,
S_LOAD, S_DATA,
V
IH
Input
S_CLOCK, nP_LOAD,
High Voltage M0:M8, N0:N1
2 VCC + 0.3
TEST_CLK
VCO_SEL, CLK_SEL, MR,
S_LOAD, S_DATA,
VIL
Input
S_CLOCK, nP_LOAD,
Low Voltage M0:M8, N0:N1
2 VCC + 0.3
-0.3 0.8
TEST_CLK
-0.3 1.3
M0-M4, M6-M8, N0, N1, MR,
IIH
Input
S_CLOCK, TEST_CLK,
High Current S_DATA, S_LOAD, nP_LOAD
VCC = VIN = 3.465V
M5, CLK_SEL, VCO_SEL
VCC = VIN = 3.465V
M0-M4, M6-M8, N0, N1, MR,
S_CLOCK, TEST_CLK,
VCC = 3.465V,
IIL
Input
S_DATA, S_LOAD, nP_LOAD
Low Current
M5, CLK_SEL, VCO_SEL
VIN = 0V
VCC = 3.465V,
VIN = 0V
-5
-150
VOH
Output
High Voltage
TEST
VCC = 3.135V,
I = -36mA
OH
2.6
VOL
Output
Low Voltage
TEST
VCC = 3.135V,
IOL = 36mA
150
5
0.5
Units
V
V
V
V
µA
µA
µA
µA
V
V
8432DYI-101
www.icst.com/products/hiperclocks.html
5
REV. A MAY 23, 2005
5 Page 
Integrated
Circuit
Systems, Inc.
ICS8432I-101
700MHZ,
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
LAYOUT GUIDELINE
The schematic of the ICS8432I-101 layout example used in
this layout guideline is shown in Figure 6A. The ICS8432I-101
recommended PCB board layout for this example is shown in
Figure 6B. This layout example is used as a general guideline.
The layout in the actual system will depend on the selected com-
ponent types, the density of the components, the density of the
traces, and the stack up of the P.C. board.
U1
1
2
3
4
M5
M6
M7
5
6
7
8
M8
N0
N1
nc
VEE
8432-101
C14
0.1u
nCLK
CLK
CLK
REF_IN
nCLK_SEL
24
23
22
21
XTAL_SEL
VDDA
S_LOAD
S_DATA
S_CLOCK
20
19
18
17
S_LOAD
S_DATA
S_CLOCK
MR
MR
VCCA
C11
0.01u
R7
10
C16
10u
Termination A
VCC
C15
0.1u
R1 R3
125 125
Zo = 50 Ohm
IN+
TL1
Zo = 50 Ohm
IN-
TL2
R2 R4
84 84
VCC
Termination B
(not shown in
the layout)
IN+
IN-
R2 R1
50 50
R3
50
FIGURE 6A. SCHEMATIC OF RECOMMENDED LAYOUT
8432DYI-101
www.icst.com/products/hiperclocks.html
11
REV. A MAY 23, 2005
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet ICS432I-101.PDF ] | |
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