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Número de pieza | NTD5P06V | |
Descripción | Power MOSFET ( Transistor ) | |
Fabricantes | ON Semiconductor | |
Logotipo | ||
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MTD5P06V
Preferred Device
Power MOSFET
5 Amps, 60 Volts
P−Channel DPAK
This Power MOSFET is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and power
motor controls, these devices are particularly well suited for bridge
circuits where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected voltage
transients.
• Avalanche Energy Specified
• IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol Value Unit
Drain−to−Source Voltage
Drain−to−Gate Voltage (RGS = 1.0 MΩ)
Gate−to−Source Voltage
− Continuous
− Non−repetitive (tp ≤ 10 ms)
Drain Current − Continuous @ 25°C
Drain Current − Continuous @ 100°C
Drain Current − Single Pulse (tp ≤ 10 µs)
Total Power Dissipation @ 25°C
Derate above 25°C
Total Power Dissipation @ TA = 25°C
(Note 2.)
VDSS
VDGR
VGS
VGSM
ID
ID
IDM
PD
60 Vdc
60 Vdc
± 15
± 25
5
4
18
40
0.27
2.1
Vdc
Vpk
Adc
Apk
Watts
W/°C
Watts
Operating and Storage Temperature Range TJ, Tstg −55 to
175
°C
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, Peak
IL = 5 Apk, L = 10 mH, RG = 25 Ω)
EAS
125 mJ
Thermal Resistance
− Junction to Case
− Junction to Ambient (Note 1.)
− Junction to Ambient (Note 2.)
RθJC
RθJA
RθJA
°C/W
3.75
100
71.4
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from Case for 10
seconds
TL
260 °C
1. When surface mounted to an FR4 board using the minimum
recommended pad size.
2. When surface mounted to an FR−4 board using the 0.5 sq.in. drain pad size.
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V(BR)DSS
60 V
RDS(on) TYP
340 mW
ID MAX
5.0 A
P−Channel
D
G
4
12
3
DPAK
CASE 369C
Style 2
4
S
MARKING DIAGRAMS
4
Drain
1
Gate
2
Drain
3
Source
4
Drain
1
2
3
DPAK
CASE 369D
Style 2
5P06V
Y
WW
Device Code
= Year
= Work Week
12 3
Gate Drain Source
ORDERING INFORMATION
Device
Package
Shipping
NTD5P06V
NTD5P06V−1
NTD5P06VT4
DPAK
DPAK
Straight Lead
75 Units/Rail
75 Units/Rail
DPAK 2500 Tape & Reel
Preferred devices are recommended choices for future use
and best overall value.
© Semiconductor Components Industries, LLC, 2003
November, 2003 − Rev. 3
1
Publication Order Number:
MTD5P06V/D
1 page MTD5P06V
10
9
8
7 Q1
6
5
QT
Q2
60
VGS 54
48
42
36
30
4 24
3 18
2 Q3
1
TJ = 25°C 12
VDS
ID = 5 A
6
00
0 2 4 6 8 10 12 14
Qg, TOTAL GATE CHARGE (nC)
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
100
TJ = 25°C
ID = 5 A
VDD = 30 V
VGS = 10 V
tr
td(off)
10
tf
td(on)
1
1 10 100
RG, GATE RESISTANCE (OHMS)
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
5
4.5 TJ = 25°C
VGS = 0 V
4
3.5
3
2.5
2
1.5
1
0.5
0
0.2
0.4 0.6 0.8 1 1.2 1.4 1.6
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
1.8
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal
Resistance−General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the
transition time (tr,tf) do not exceed 10 µs. In addition the total
power averaged over a complete switching cycle must not
exceed (TJ(MAX) − TC)/(RθJC).
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry
custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 12). Maximum
energy at currents below rated continuous ID can safely be
assumed to equal the values indicated.
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NTD5P06V | Power MOSFET ( Transistor ) | ON Semiconductor |
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