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PDF EM78P311N Data sheet ( Hoja de datos )
| Número de pieza | EM78P311N | |
| Descripción | 8-BIT Microcontroller | |
| Fabricantes | ELAN Microelectronics | |
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EM78P311N
8-BIT
Microcontroller
Green Product
Specification
DOC. VERSION 1.0
ELAN MICROELECTRONICS CORP.
October 2006
1 page  
EM78P311N
8-Bit Microcontroller
1 General Description
The EM78P311N is an 8-bit microprocessor with low-power, high-speed CMOS technology and high noise immunity. It
has an on-chip 2K×13-bits Electrical One Time Programmable Read Only Memory (OTP-ROM). It provides
multi-protection bits to prevent intrusion of user’s OTP memory codes. Seven Option bits are also available to meet
user’s requirements. With its OTP-ROM feature, the EM78P311N provides a convenient way of developing and verifying
user’s programs. Moreover, this OTP device offers the advantages of easy and effective program updates, using
development and programming tools. User can avail of the ELAN Writer to easily program his development code.
2 Features
CPU configuration
z 2K×13 bits on-chip ROM
z 80×8 bits on-chip registers (SRAM)
z 8-level stacks for subroutine nesting
z Less than 3.5mA at 5V/8MHz
z Typically 0.8 μA, during sleep mode
z Typically 1.1 μA, during idle mode
I/O port configuration
z 4 bidirectional I/O ports : P6, P7, P8, P9
z 22 I/O pins
z 10 Programmable pull-down I/O pins
z 10 programmable pull-high I/O pins
z External interrupt : P60, P61, P73, P80
Operating voltage range:
z OTP version
Operating voltage range:2.5v~5.5v
Operating temperature range:
z -40~85°C
Operating frequency range:
Main clock
• Crystal mode:
DC ~ 20MHz/2clks @ 5V; DC ~100ns inst. cycle @ 5V
DC ~ 8MHz/2clks @ 3V;DC ~ 250ns inst. cycle @ 3V
• ERC mode:
DC ~ 16MHz/2clks @ 5V;DC ~ 125ns inst. cycle @ 5V
DC ~ 8MHz/2clks @ 3V;DC ~ 250ns inst. cycle @ 3V
Peripheral configuration
z Serial peripheral interface (SPI) available
z Universal asynchronous receiver transmitter interface
(UART)available
z 16 bits Counter/Timer
TC2: Timer/Counter/Window
z 8 bits Timer/Counter
TCC: 8-bit real time clock/counter with overflow
interrupt
TC3: Timer/Counter/Capture
TC4: Timer/Counter/ PWM (pulse width
modulation)/PDO (Programmable divider output)
z 8-bit channels Analog-to-Digital Converter with 10-bit
resolution
z Time Base Timer:(1Hz~16kHz at 8MHz)
z Key tone output:(1kHz~8kHz at 8MHz)
z 8-bit channels Analog-to-Digital Converter with 10-bit
resolution
Fifteen available interruptions:
z WDT time-out interrupt
z TCC overflow interrupt
z Time base timer interrupt(the first falling edge of the
source clock)
z Serial UART transmit interrupt
z Serial UART receive interrupt
z Serial UART receive error interrupt
z Four External interrupt
z ADC completion interrupt
z TC2 overflow interrupt
z TC3 overflow interrupt
z TC4 overflow interrupt
z Serial SPI interrupt
Special features
z Programmable free running watchdog timer
z Two clocks per instruction cycle
z Power on Reset
z High noise immunity
z Power saving Sleep mode
z Selectable Oscillation mode
Package type:
z 28-pin DIP 600 mil: EM78P311NP
z 28-pin Skinny DIP 300 mil: EM78P311NAK
z 28-pin Skinny DIP 400 mil: EM78P311N
z 28-pin SOP 300 mil: EM78P311NM
z 28-pin SSOP 209 mil: EM78P311NS
3 Pin Assignment
(ACLK) OSCO
OSCI
TEST
(AD0) P90
(AD1) P91
(AD2) P92
(AD3) P93
(AD4) P94
(AD5) P95
(AD6) P96
(AD7/VREF) P97
(TC3, INT3) P80
(TC4, /PWM, /PDO) P81
VSS
1 28
2 27
3 26
4 25
5 24
6 23
7 22
8 21
9 20
10 19
11 18
12 17
13 16
14 15
EM78P311N
VDD
/RESET (VPP)
P67 (DINCK)
P66 (DATAIN)
P65 (PGMB)
P64 (/SS)(OEB)
P63 (/TONE)
P62 (TC2)
P61 (INT1)
P60 (/INT0)
P73 (/SLEEP, /INT5)
P72 (TX,SO)
P71(RX,SI)
P70 (/SCK)
Fig. 3- Pin Assignment
Product Specification (V1.0) 10.02.2006
(This specification is subject to change without further notice)
•1
5 Page 
EM78P311N
8-Bit Microcontroller
Bit 3 (P): Power down bit. Set to “1” during power on or by a "WDTC" command and
reset to “0” by a "SLEP" command.
Bit 2 (Z): Zero flag. Set to "1" if the result of an arithmetic or logic operation is
zero.
Bit 1 (DC) : Auxiliary carry flag
Bit 0 (C) : Carry flag
R4 (RAM Select Register)
Bit 7
GRBS1
Bit 6
RBS0
Bit 5
RSR5
Bit 4
RSR4
Bit 3
RSR3
Bit 2
RSR2
Bit 1
RSR1
Bit 0
RSR0
Bit 7: 6 ( GRBS1: GRBS0 ): determine which general purpose banks are activated
among the two banks. Use BANK instruction (e.g. BABK 1) to change bank.
GRBS1
0
0
GRBS0
0
1
General Purpose Register Bank (Address 20H ~ 3FH)
Bank 0
Bank 1
Bit 5: 0 ( RSR5 : RSR0 ): used to select the registers (Address: 00h~3Fh) in indirect
addressing mode. If no indirect addressing is used, the RSR can be used as
an 8-bit general-purpose read/write register. See the data memory
configuration in Fig. 5-2.
R5 (System Control Register)
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
PS0
Bit 3
0
Bit 2
1
Bit 1
SIS
Bit 0
REM
Bit 4 (PS0): ROM Page select bits. User can use PAGE instruction (e.g. PAGE 1) or set
PS0 bits to change the ROM page. When executing a "JMP", "CALL", or other
instructions which cause the program counter to change (e.g. MOV R2, A),
PS0 are loaded into the 11th bit of the program counter and select one of the
available program memory pages. Note that RET (RETL, RETI) instruction
does not change the PS0 bits. That is, return will always be to the page from
where the subroutine was called, regardless of the PS0 bits current setting.
PS0 Program Memory Page [Address]
0 Page 0 [0000~03FF]
1 Page 1 [0400~07FF]
Bit 1 ( SIS ) : Sleep and Idle mode select
SIS = “0” : Idle mode
SIS = “1” : Sleep mode
Bit 0 ( REM ) : Release method for sleep mode
REM = “0” : /SLEEP pin input rising edge released
REM = “1” : /SLEEP pin input “H” level released
Product Specification (V1.0) 10.02.2006
(This specification is subject to change without further notice)
•7
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