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PDF WM8804 Data sheet ( Hoja de datos )
| Número de pieza | WM8804 | |
| Descripción | 1:1 Digital Interface Transceiver | |
| Fabricantes | Wolfson Microelectronics | |
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WM8804
1:1 Digital Interface Transceiver with PLL
DESCRIPTION
The WM8804 is a high performance consumer mode
S/PDIF transceiver with support for 1 received channel and
1 transmitted channel.
A crystal derived, or externally provided high quality master
clock is used to allow low jitter recovery of S/PDIF supplied
master clocks.
Generation of all typically used audio clocks is possible
using the high performance internal PLL. A dedicated
CLKOUT pin provides a high drive clock output.
A pass through option is provided which allows the device
simply to be used to clean up (de-jitter) the received digital
audio signals.
The device may be used under software control or stand
alone hardware control modes. In software control mode,
both 2-wire with read back and 3-wire interface modes are
supported.
Status and error monitoring is built-in and results can be
read back over the control interface, on the GPO pins or
streamed over the audio data interface in ‘With Flags’ mode
(audio data with status flags appended).
The audio data interface supports I2S, left justified, right
justified and DSP audio formats of 16-24 bit word length,
with sample rates from 32 to 192ks/s.
The device is supplied in a 20-lead Pb-free SSOP package.
BLOCK DIAGRAM
FEATURES
• S/PDIF (IEC60958-3) compliant.
• Advanced jitter attenuating PLL with low intrinsic period
jitter of 50 ps RMS.
• S/PDIF recovered clock using PLL, or stand alone crystal
derived clock generation.
• Supports 10 – 27MHz crystal clock frequencies.
• 2-wire / 3-Wire serial or hardware control interface.
• Programmable audio data interface modes:
- I2S, Left, Right Justified or DSP
- 16/20/24 bit word lengths
• 1 channel receiver input and 1 channel transmit output.
• Auto frequency detection / synchronisation.
• Selectable output status data bits.
• Up to 3 configurable GPO pins.
• De-emphasis flag output.
• Non-audio detection including DOLBYTM and DTSTM.
• Channel status changed flag.
• Configurable clock distribution with selectable output
MCLK rate of 512fs, 256fs, 128fs and 64fs.
• 2.7 to 3.6V digital and PLL supply voltages.
• 20-lead SSOP package.
APPLICATIONS
• AV processors and Hi-Fi systems
• Music industry applications
• DVD-P/DVD-RW
• Digital TV
WOLFSON MICROELECTRONICS plc
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Production Data, March 2009, Rev 4.5
Copyright ©2009 Wolfson Microelectronics plc
1 page  
Production Data
WM8804
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at
or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage
conditions prior to surface mount assembly. These levels are:
MSL1 = unlimited floor life at <30°C / 85% Relative Humidity. Not normally stored in moisture barrier bag.
MSL2 = out of bag storage for 1 year at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
MSL3 = out of bag storage for 168 hours at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
The Moisture Sensitivity Level for each package type is specified in Ordering Information.
CONDITION
Digital core and I/O buffer supply voltage
PLL supply voltage
Voltage range digital inputs
Master Clock Frequency
Operating temperature range, TA
Storage temperature
Note:
1. PLL and digital supplies must always be within 0.3V of each other.
2. PLL and digital grounds must always be within 0.3V of each other.
MIN
-0.3V
-0.3V
DGND -0.3V
-40°C
-65°C
MAX
+5V
+5V
DVDD +0.3V
37MHz
+85°C
+150°C
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PD, Rev 4.5, March 2009
5
5 Page 
Production Data
WM8804
DEVICE DESCRIPTION
INTRODUCTION
FEATURES
• IEC-60958-3 compatible with 32 to 192k frames/s support.
• Supports AES-3 data frames.
• Support for reception and transmission of S/PDIF data.
• Clock synthesis PLL with reference clock input and low jitter output.
• Supports input reference clock frequencies from 10MHz to 27MHz.
• Dedicated high drive clock output pin.
• Register controlled channel status bit configuration.
• Register read-back of recovered channel status bits and error flags.
• Detection of non-audio data, sample rate and de-emphasis.
• Programmable GPOs for error flags and frame status flags.
The WM8804 is an IEC-60958 compatible S/PDIF transceiver with support for one received S/PDIF
data stream and one transmitted S/PDIF data stream.
The receiver performs data and clock recovery, and transmits recovered data from the chip either
through the digital audio interface or, alternatively, the device can loop the received S/PDIF data
back out through the S/PDIF transmitter producing a de-jittered S/PDIF transmit data stream. The
recovered clock may be routed to a high drive output pin for external use. If there is no S/PDIF input
data stream the PLL can be configured to output all standard MCLK frequencies or it can be
configured to maintain the frequency of the last received S/PDIF data stream.
The transmitter generates S/PDIF frames where audio data may be sourced from the S/PDIF
receiver or the digital audio interface. Timing for the S/PDIF transmitter interface can be sourced
from the internally derived MCLK in loop through mode or it can be taken from an external source.
S/PDIF FORMAT
S/PDIF is a serial, bi-phase-mark encoded data stream. An S/PDIF frame consists of two sub-
frames. Each sub-frame is made up of:
• Preamble – a synchronization pattern used to identify the start of a 192-frame block or sub-
frame
• 4-bit Auxiliary Data (AUX) – ordered LSB to MSB
• 20-bit Audio Data (24-bit when combined with AUX) – ordered LSB to MSB
• Validity Bit – a 1 indicates invalid data in the associated sub-frame
• User Bit – over 192-frames, this forms a User Data Block
• Channel Bit – over 192-frames, this forms a Channel Status Block
• Parity Bit – used to maintain even parity over the sub-frame (not including the preamble)
An S/PDIF Block consists of 192 frames. Channel and user blocks are incorporated within the 192-
frame S/PDIF Block. For Consumer mode only the first 40-frames are used to make up the Channel
and User blocks. Figure 6 illustrates the S/PDIF format. The WM8804 does not support transmission
of user channel data. Received user channel data may be accessed via GPO pins.
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PD, Rev 4.5, March 2009
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet WM8804.PDF ] | |
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