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PDF IDT70T3539M Data sheet ( Hoja de datos )
| Número de pieza | IDT70T3539M | |
| Descripción | HIGH-SPEED 2.5V 512K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM | |
| Fabricantes | IDT | |
| Logotipo |  |
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HIGH-SPEED 2.5V
512K x 36
SYNCHRONOUS
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
PRELIMINARY
IDT70T3539M
Features:
◆ True Dual-Port memory cells which allow simultaneous
access of the same memory location
◆ High-speed data access
– Commercial: 3.6ns (166MHz)/4.2ns (133MHz)(max.)
– Industrial: 4.2ns (133MHz) (max.)
◆ Selectable Pipelined or Flow-Through output mode
◆ Counter enable and repeat features
◆ Dual chip enables allow for depth expansion without
additional logic
◆ Interrupt and Collision Detection Flags
◆ Full synchronous operation on both ports
– 6ns cycle time, 166MHz operation (12Gbps bandwidth)
– Fast 3.6ns clock to data out
– 1.5ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 166MHz
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
◆ Separate byte controls for multiplexed bus and bus
matching compatibility
◆ Dual Cycle Deselect (DCD) for Pipelined Output Mode
◆ 2.5V (±100mV) power supply for core
◆ LVTTL compatible, selectable 3.3V (±150mV) or 2.5V
(±100mV) power supply for I/Os and control signals on
each port
◆ Includes JTAG functionality
◆ Industrial temperature range (-40°C to +85°C) is
available at 133MHz
◆ Available in a 256-pin Ball Grid Array (BGA)
Functional Block Diagram
BE3L
BE2L
B E1 L
BE0L
BE3R
BE2R
BE1R
BE0R
FT/PIP EL
0a 1a
1/0
a
0b 1b 0c 1c
bc
0d 1d
d
1d 0d
d
1c 0c
c
1b 0b
b
1a 0a
1/0
a
FT/PIPER
R/WL
R/WR
CE0L
CE1L
OEL
1
0
1/0
FT/PIPEL
1d 0d 1c 0c 1b 0b 1a 0a
0/1
a bc d
BBBBB BBB
WWWWW WWW
01233 210
L L L L R RRR
D ou t0-8_ L
D ou t9-17 _L
D ou t18-2 6_L
D ou t27-3 5_L
D ou t0-8_ R
Do ut9 -17_ R
D out 18- 26 _R
D out 27- 35 _R
512K x 36
MEMORY
ARRAY
0a 1a 0b 1b 0c 1c 0d 1d
d c ba
0/1
CE0R
1 CE1R
0
1/0
OER
FT/PIPER
,
I/O0L - I/O35L
Din_L
Din_R
I/O0R - I/O35R
CLKL
A18L
A0L
RE PEATL
ADSL
CN TENL
Counter/
Address
Reg.
ADDR_L
ADDR_R
Counter/
Address
Reg.
A18R
CLKR
A0R
REPEATR
ADSR
CNTENR
COL L
INTL
CE 0 L
CE1L
R/WL
INTERRUPT
COL LISION
DE TE CTION
LOGIC
CE0 R
CE1 R
R /W R
COLR
INTR
TDI
TDO
Z ZL(1 )
ZZ
CONTROL
LOGIC
ZZR(1)
NOTE:
1. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and OPTx and
the sleep mode pins themselves (ZZx) are not affected during sleep mode.
©2004 Integrated Device Technology, Inc.
1
,
JTAG
TCK
TMS
TRST
5678 drw 01
APRIL 2004
DSC 5678/5
1 page  
IDT70T3539M
High-Speed 2.5V 512K x 36 Dual-Port Synchronous Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Truth Table I—Read/Write and Enable Control (1,2,3,4)
OE CLK CE0 CE1 BE3 BE2 BE1 BE0 R/W ZZ
Byte 3
I/O27-35
Byte 2
I/O18-26
Byte 1
I/O9-17
Byte 0
I/O0-8
MODE
X↑
HX
XXXXX
L
High-Z
High-Z
High-Z
High-Z Deselected–Power Down
X
↑
X
L
X
X
X
X
X
L
High-Z
High-Z
High-Z
High-Z Deselected–Power Down
X↑
L
HHHHHX
L
High-Z
High-Z
High-Z
High-Z All Bytes Deselected
X↑
L
HHHHL
L
L
High-Z
High-Z
High-Z
DIN Write to Byte 0 Only
X
↑
L
HHH
L
H
L
L
High-Z
High-Z
DIN
High-Z Write to Byte 1 Only
X ↑ L H H L H H L L High-Z
DIN
High-Z
High-Z Write to Byte 2 Only
X↑L HL HHHL L
DIN
High-Z
High-Z
High-Z Write to Byte 3 Only
X
↑
L
HHH
L
L
L
L
High-Z
High-Z
DIN
DIN Write to Lower 2 Bytes Only
X↑L HL L HHL L
DIN
DIN
High-Z
High-Z Write to Upper 2 bytes Only
X↑LHL L L L L L
DIN
DIN
DIN
DIN Write to All Bytes
L↑L
HHHHL
H
L
High-Z
High-Z
High-Z
DOUT Read Byte 0 Only
L↑L
HHHL HH L
High-Z
High-Z
DOUT
High-Z Read Byte 1 Only
L↑L
HHL
HHH
L
High-Z
DOUT
High-Z
High-Z Read Byte 2 Only
L↑L HL HHHH L
DOUT
High-Z
High-Z
High-Z Read Byte 3 Only
L↑L
HHHL
L
H
L
High-Z
High-Z
DOUT
DOUT Read Lower 2 Bytes Only
L↑L HL L HHH L
DOUT
DOUT
High-Z
High-Z Read Upper 2 Bytes Only
L↑LHL L L L HL
DOUT
DOUT
DOUT
DOUT Read All Bytes
H↑
X
X
X
X
X
X
X
L
High-Z
High-Z
High-Z
High-Z Outputs Disabled
X
X
X
X
X
X
X
X
X
H
High-Z
High-Z
High-Z
High-Z Sleep Mode
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, REPEAT = VIH.
3. OE and ZZ are asynchronous input signals.
4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.
5678 tbl 02
Truth Table II—Address Counter Control (1,2)
Address
Previous
Internal
Address
Internal
Address
Used
CLK
ADS CNTEN REPEAT(6)
I/O(3)
MODE
An X An ↑ L(4) X H DI/O (n) External Address Used
X
An
An + 1
↑
H
L(5)
H DI/O(n+1) Counter Enabled—Internal Address generation
X
An + 1 An + 1
↑
H
H
H DI/O(n+1) External Address Blocked—Counter disabled (An + 1 reused)
X
X
An ↑ X X
L(4) DI/O(n) Counter Set to last valid ADS load
NOTES:
5678 tbl 03
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. Read and write operations are controlled by the appropriate setting of R/W, CE0, CE1, BEn and OE.
3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle.
4. ADS and REPEAT are independent of all other memory control signals including CE0, CE1 and BEn
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, BEn.
6. When REPEAT is asserted, the counter will reset to the last valid address loaded via ADS. This value is not set at power-up: a known location should be loaded
via ADS during initialization if desired. Any subsequent ADS access during operations will update the REPEAT address location.
6.452
5 Page 
IDT70T3539M
High-Speed 2.5V 512K x 36 Dual-Port Synchronous Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle for Pipelined Operation
(FT/PIPE'X' = VIH)(1,2)
tCH2
tCYC2
tCL2
CLK
CE0
CE1
BEn
tSC tHC
tSB tHB
tSB tHB
(5)
tSC tHC
(3)
R/W
ADDRESS(4)
DATAOUT
(1)
OE
tSW tHW
tSA tHA
An
An + 1
(1 Latency)
tCD2
tCKLZ (1)
An + 2
tDC
Qn
An + 3
Qn + 1
tOHZ
tOLZ
Qn + 2 (5)
tOE
,
5678 drw 05
Timing Waveform of Read Cycle for Flow-through Output
(FT/PIPE"X" = VIL)(1,2,6)
tCYC1
tCH1
tCL1
CLK
CE0
CE1
BEn
tSC tHC
tSB tHB
tSC tHC
(3)
tSB tHB
R/W
ADDRESS(4)
DATAOUT
tSW tHW
tSA tHA
An
tCD1
tCKLZ
An + 1
tDC
Qn
An + 2
Qn + 1
tOHZ
An + 3
tCKHZ
Qn + 2(5)
tOLZ
tDC
OE (1)
NOTES:
tOE
5678 drw 06
1. OE is asynchronously controlled; all other inputs depicted in the above waveforms are synchronous to the rising clock edge.
2. ADS = VIL, CNTEN and REPEAT = VIH.
3. The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL, BEn = VIH following the next rising edge of the clock. Refer to
Truth Table 1.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
5. If BEn was HIGH, then the appropriate Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state).
6. "x" denotes Left or Right port. The diagram is with respect to that port.
,
6.1412
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet IDT70T3539M.PDF ] | |
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