|
|
PDF IDT70T3509M Data sheet ( Hoja de datos )
| Número de pieza | IDT70T3509M | |
| Descripción | HIGH-SPEED 2.5V 1024K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM | |
| Fabricantes | IDT | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de IDT70T3509M (archivo pdf) en la parte inferior de esta página. Total 23 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
HIGH-SPEED 2.5V
1024K x 36
SYNCHRONOUS
IDT70T3509M
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
Features:
◆ True Dual-Port memory cells which allow simultaneous
access of the same memory location
◆ High-speed data access
– Commercial: 4.2ns (133MHz)(max.)
– Industrial: 4.2ns (133MHz)(max.)
◆ Selectable Pipelined or Flow-Through output mode
◆ Counter enable and repeat features
◆ Interrupt Flags
◆ Full synchronous operation on both ports
– 7.5ns cycle time, 133MHz operation (9.5Gbps bandwidth)
– 1.5ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 133MHz
– Fast 4.2ns clock to data out
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
◆ Separate byte controls for multiplexed bus and bus
matching compatibility
◆ Dual Cycle Deselect (DCD) for Pipelined Output Mode
◆ 2.5V (±100mV) power supply for core
◆ LVTTL compatible, selectable 3.3V (±150mV) or 2.5V
(±100mV) power supply for I/Os and control signals on
each port
◆ Includes JTAG functionality
◆ Available in a 256-pin Ball Grid Array (BGA)
◆ Common BGA footprint provides design flexibility over
seven density generations (512K to 36M-bit)
◆ Green parts available, see ordering information
Functional Block Diagram
BE3L
BE3R
BE2L
BE2R
BE1L
BE1R
BE0L
BE0R
FT/PIPEL
R/WL
(2)
CE0L
CE1L
OEL
FT/PIPEL
0a 1a
1/0
a
0b 1b 0c 1c
bc
0d 1d
d
1
0
1 /0
B B BBB B BB
W W WWW W WW
0 1 233 2 10
L L LL RRRR
Dou t0-8_ L
Dou t9-17 _L
Dou t18-2 6_L
Dou t27-3 5_L
Dout0- 8_R
Dout 9-1 7_R
Dout18-26_R
Dout27-35_R
1d 0d 1c 0c 1b 0b 1a 0a
0 /1
ab cd
1024K x 36
MEMORY
A RR AY
I/O0L - I/O35L
CLKL
A19L
A0L
REPEATL
ADSL
CNTENL
INTL
Din_L
Din_R
Counter/
Address
Reg.
CE 0 L
CE1L
R/ W L
ADDR_L
ADDR_R
INTERRUPT
LOGIC
ZZL(1)
ZZ
CONTROL
LO GI C
1d 0d
d
1c 0c
c
1b 0b
b
1a 0a
1 /0
a
1
0
1/0
FT/PIPER
R/WR
(2)
CE0R
CE1R
OER
0a 1a 0b 1b 0c 1c 0d 1d
dcba
0/1
FT/PIPER
,
C o unt er/
Address
Reg.
CE0 R
CE1R
R/ WR
ZZR(1)
I/O0R - I/O35R
A19R
CLKR
A 0R
REPEATR
ADSR
CNTENR
TDI
TDO
INTR
,
JTAG
TCK
TMS
TRST
5682 drw 01
NOTE:
1. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and OPTx
and the sleep mode pins themselves (ZZx) are not affected during sleep mode.
2. See Truth Table I for Functionality.
©2007 Integrated Device Technology, Inc.
1
AUGUST 2007
DSC 5682/7
1 page  
IDT70T3509M
High-Speed 2.5V 1024K x 36 Dual-Port Synchronous Static RAM
Commercial Temperature Range
Truth Table I—Read/Write and Enable Control (1,2,3,4)
OE CLK CE0 CE1 BE3 BE2 BE1 BE0 R/W ZZ
Byte 3
I/O27-35
Byte 2
I/O18-26
Byte 1
I/O9-17
Byte 0
I/O0-8
MODE
X↑
HL
X
X
X
X
X
L
High-Z
High-Z
High-Z
High-Z Deselected–Power Down
X ↑ L L X X X X X X Active Active Active Active Not Allowed
X ↑ H H X X X X X X Active Active Active Active Not Allowed
X↑
L
HHHHHX
L
High-Z
High-Z
High-Z
High-Z All Bytes Deselected
X↑
L
HHHHL
L
L
High-Z
High-Z
High-Z
DIN Write to Byte 0 Only
X↑
L
HHHL
H
L
L
High-Z
High-Z
DIN
High-Z Write to Byte 1 Only
X ↑ L H H L H H L L High-Z DIN High-Z High-Z Write to Byte 2 Only
X ↑ L H L H H H L L DIN High-Z High-Z High-Z Write to Byte 3 Only
X↑
L
HHHL
L
L
L
High-Z
High-Z
DIN
DIN Write to Lower 2 Bytes Only
X↑L HL L HHL L
DIN
DIN High-Z High-Z Write to Upper 2 bytes Only
X↑LHL L L L L L
DIN
DIN
DIN
DIN Write to All Bytes
L↑
L
HHHHL
H
L
High-Z
High-Z
High-Z
DOUT Read Byte 0 Only
L↑
L
HHHL
HH
L
High-Z
High-Z
DOUT
High-Z Read Byte 1 Only
L ↑ L H H L H H H L High-Z DOUT High-Z High-Z Read Byte 2 Only
L↑L HL HHHH L
DOUT
High-Z High-Z High-Z Read Byte 3 Only
L↑
L
HHHL
L
H
L
High-Z
High-Z
DOUT
DOUT Read Lower 2 Bytes Only
L↑L HL L HHH L
DOUT
DOUT
High-Z High-Z Read Upper 2 Bytes Only
L↑LHL L L L HL
DOUT
DOUT
DOUT
DOUT Read All Bytes
H↑
X
X
X
X
X
X
X
L
High-Z
High-Z
High-Z
High-Z Outputs Disabled
X X X X X X X X X H High-Z High-Z High-Z High-Z Sleep Mode
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, REPEAT = VIH.
3. OE and ZZ are asynchronous input signals.
4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.
5682 tbl 02
Truth Table II—Address Counter Control (1,2)
Address
Previous
Internal
Address
Internal
Address
Used
CLK
ADS CNTEN REPEAT(6)
I/O(3)
MODE
An X An ↑ L(4) X H DI/O (n) External Address Used
X
An
An + 1
↑
H
L(5)
H DI/O(n+1) Counter Enabled—Internal Address generation(7)
X
An + 1 An + 1
↑
H
H
H DI/O(n+1) External Address Blocked—Counter disabled (An + 1 reused)
X
X
An ↑ X X
L(4) DI/O(n) Counter Set to last valid ADS load
NOTES:
5682 tbl 03
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. Read and write operations are controlled by the appropriate setting of R/W, CE0, CE1, BEn and OE.
3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle.
4. ADS and REPEAT are independent of all other memory control signals including CE0, CE1 and BEn
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, BEn.
6. When REPEAT is asserted, the counter will reset to the last valid address loaded via ADS. This value is not set at power-up: a known location should be loaded
via ADS during initialization if desired. Any subsequent ADS access during operations will update the REPEAT address location.
7. Address A19 must be managed as part of a full depth counter implementation using the IDT70T3509M. For physical addresses 00000H through 7FFFFH the value
of a A19 is 0, while for physical addresses 80000H through FFFFFH the value of A19 is 1. The user needs to keep track of the device counter and make sure that
A19 is actively driven from 0-to-1 or 1-to-0 and held as needed at the appropriate address boundaries for full depth counter operation and that A19 is in the appropriate
state when using the REPEAT function.
6.452
5 Page 
IDT70T3509M
High-Speed 2.5V 1024K x 36 Dual-Port Synchronous Static RAM
Commercial Temperature Range
Timing Waveform of Read Cycle for Pipelined Operation
(FT/PIPE'X' = VIH)(1,2)
tCH2
tCYC2
tCL2
CLK
CE0
CE1
BEn
tSC tHC
tSB tHB
tSB tHB
(5)
tSC tHC
(3)
R/W
ADDRESS(4)
DATAOUT
(1)
OE
tSW tHW
tSA tHA
An
An + 1
(1 Latency)
tCD2
tCKLZ (1)
An + 2
tDC
Qn
An + 3
Qn + 1
tOHZ
tOLZ
Qn + 2 (5)
tOE
,
5682 drw 05
Timing Waveform of Read Cycle for Flow-Through Output
(FT/PIPE"X" = VIL)(1,2,6)
tCYC1
tCH1
tCL1
CLK
CE0
CE1
BEn
tSC tHC
tSB tHB
tSC tHC
(3)
tSB tHB
R/W
ADDRESS(4)
DATAOUT
tSW tHW
tSA tHA
An
tCD1
tCKLZ
An + 1
tDC
Qn
An + 2
Qn + 1
tOHZ
An + 3
tCKHZ
Qn + 2(5)
tOLZ
tDC
OE (1)
NOTES:
tOE
5682 drw 06
1. OE is asynchronously controlled; all other inputs depicted in the above waveforms are synchronous to the rising clock edge.
2. ADS = VIL, CNTEN and REPEAT = VIH.
3. The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL, BEn = VIH following the next rising edge of the clock. Refer to
Truth Table 1.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
5. If BEn was HIGH, then the appropriate Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state).
6. "x" denotes Left or Right port. The diagram is with respect to that port.
,
6.1412
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet IDT70T3509M.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| IDT70T3509M | HIGH-SPEED 2.5V 1024K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM | IDT |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |