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PDF IDT70P34L Data sheet ( Hoja de datos )
| Número de pieza | IDT70P34L | |
| Descripción | (IDT70P24L - IDT70P35) HIGH-SPEED 1.8V 8/4K x 18 DUAL-PORT | |
| Fabricantes | IDT | |
| Logotipo |  |
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HIGH-SPEED 1.8V
8/4K x 18 DUAL-PORT
8/4K x 16 DUAL-PORT
STATIC RAM
ADVANCED
IDT70P35/34L
IDT70P25/24L
Features
◆ True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
◆ High-speed access
IDT70P35/34L (IDT70P25/24L)
– Commercial: 20/25ns (max.)
– Industrial: 25ns (max.)
◆ Low-power operation
IDT70P35/34L (IDT70P25/24L)
Active: 30.6mW (typ.)
Standby: 5.4mW (typ.)
◆ Separate upper-byte and lower-byte control for multiplexed
bus compatibility
◆ IDT70P35/34L (IDT70P25/24L) easily expands data bus
width to 36 bits (32 bits) or more using the Master/Slave
select when cascading more than one device
◆ M/S = VIH for BUSY output flag on Master
M/S = VIL for BUSY input on Slave
◆ BUSY and Interrupt Flag
◆ On-chip port arbitration logic
◆ Full on-chip hardware support of semaphore signaling
between ports
◆ Fully asynchronous operation from either port
◆ LVTTL-compatible, single 1.8V (±100mV) power supply
◆ Available in a 100-pin Thin Quad Flatpack (TQFP) package,
100-pin 0.8mm pitch Ball Grid Array (fpBGA), and 100-pin
0.5mm pitch BGA (fpBGA)
◆ Industrial temperature range (-40°C to +85°C) is available
for selected speeds
Functional Block Diagram
R/WL
UBL
R/WR
UBR
LB
CELL
OEL
LBR
CER
OER
I/O9L-I/O17L(5)
I/O0L-I/O8L(4)
BUSYL(2,3)
A12L(1)
A0L
I/O
Control
I/O
Control
Address
Decoder
13
CEL
OEL
R/WL
MEMORY
ARRAY
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
13
SEML
INTL(3)
NOTES:
1. A12 is a NC for IDT70P34 and IDT70P24.
2. (MASTER): BUSY is output; (SLAVE): BUSY is input.
3. BUSY outputs and INT outputs are non-tri-stated push-pull.
4. I/O0x - I/O7x for IDT70P25/24.
5. I/O8x - I/O15x for IDT70P25/24.
©2004 Integrated Device Technology, Inc.
M/S
1
Address
Decoder
CER
OER
R/WR
,
I/O9R-I/O17R(5)
I/O0R-I/O8R(4)
BUSYR (2,3)
A12R(1)
A0R
SEMR
INTR(3)
5683 drw 01
FEBRUARY 2004
DSC-5683/2
1 page  
IDT70P35/34L (IDT70T25/24L)
High-Speed 1.8V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
ADVANCED
Industrial and Commercial Temperature Ranges
IDT70P25/24 Pin Configurations(cont'd) (1,2,3,4)
IDT70P25/24BF
BF100(5)
12/16/03
A1
A6R
A2
A9R
100-Pin fpBGA
Top View(6)
A3 A4 A5 A6 A7
A12R(1) CER VSS VSS VSS
A8 A9 A10
I/O12R I/O9R I/O7R
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10
NC NC A8R A10R SEMR R/WR OER I/O11R I/O8R I/O6R
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10
A3R A4R A5R A7R UBR I/O15R I/O14R I/O10R NC I/O3R
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
A1R INTR A2R NC A11R LBR I/O13R NC I/O5R I/O1R
E1 E2 E3 E4 E5 E6 E7 E8 E9 E10
M/S BUSYR A0R A1L VSS VSS I/O4R I/O2R I/O0R VDD
F1 F2 F3 F4 F5 F6 F7 F8 F9 F10
VSS BUSYL A0L NC VDD VSS VDD I/O13L I/O14L I/O15L
G1 G2 G3 G4 G5 G6 G7 G8 G9 G10
INTL A3L A6L NC VSS I/O3L NC I/O11L VSS I/O12L
H1 H2 H3 H4 H5 H6 H7 H8 H9 H10
A2L A5L A10L LBL CEL I/O1L I/O7L NC NC I/O10L
J1 J2 J3 J4 J5 J6 J7 J8 J9 J10
A4L A8L A11L SEML R/WL OEL I/O4L I/O6L VSS I/O9L
K1 K2 K3 K4 K5 K6 K7 K8 K9 K10
A7L A9L A12L(1) UBL VDD VDD I/O0L I/O2L I/O5L I/O8L
NOTES:
1. A12 is a NC for IDT70P24.
2. All VDD pins must be connected to power supply.
3. All VSS pins must be connected to ground.
4. BF-100 package body is approximately 10mm x 10mm x 1.4mm with 0.8mm ball pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part marking.
5683 drw 05
,
6.542
5 Page 
IDT70P35/34L (IDT70T25/24L)
High-Speed 1.8V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
ADVANCED
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
70P35/34L20
(70P25/24L20)
Com'l Only
Symbol
READ CYCLE
Parameter
Min.
Max.
70P35/34L25
(70P25/24L25)
Com'l
& Ind
Min.
Max.
Unit
tRC Read Cycle Time
tAA Address Access Time
20 ____ 25 ____ ns
____ 20 ____ 25 ns
tACE Chip Enable Access Time(3)
____ 20 ____ 25 ns
tABE Byte Enable Access Time(3)
____ 20 ____ 25 ns
tAOE Output Enable Access Time(3)
____ 12 ____ 13 ns
tOH Output Hold from Address Change
3 ____ 3 ____ ns
tLZ Output Low-Z Time(1,2)
3 ____ 3 ____ ns
tHZ Output High-Z Time(1,2)
____ 12 ____ 15 ns
tPU Chip Enable to Power Up Time(1,2)
0 ____ 0 ____ ns
tPD Chip Disable to Power Down Time(1,2)
____ 20 ____ 25 ns
tSOP Semaphore Flag Update Pulse (OE or SEM)
10 ____
10 ____ ns
tSAA Semaphore Address Access(3)
____ 20 ____ 25 ns
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 1).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL, UB or LB = VIL, and SEM = VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL.
5683 tbl 11
Waveform of Read Cycles(5)
ADDR
CE
OE
UB, LB
tAA (4)
tACE (4)
tAOE (4)
tABE(4)
tRC
R/W
DATAOUT
tLZ (1)
VALID DATA(4)
tOH
BUSYOUT
tBDD (3,4)
tHZ(2)
,
5683 drw 09
NOTES:
1. Timing depends on which signal is asserted last, OE, CE, LB, or UB.
2. Timing depends on which signal is de-asserted first, CE, OE, LB, or UB.
3. tBDD delay is required only in case where opposite port is completing a write operation to the same address location for simultaneous read operations BUSY has no
relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tABE, tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
61.412
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet IDT70P34L.PDF ] | |
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