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Número de pieza | IDT2305B | |
Descripción | 3.3V ZERO DELAY CLOCK BUFFER | |
Fabricantes | IDT | |
Logotipo | ||
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IDT2305B
3.3V ZERO DELAY CLOCK BUFFER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
3.3V ZERO DELAY
CLOCK BUFFER
IDT2305B
FEATURES:
• Phase-Lock Loop Clock Distribution
• 10MHz to 133MHz operating frequency
• Distributes one clock input to one bank of five outputs
• Zero Input-Output Delay
• Output Skew < 250ps
• Low jitter <200 ps cycle-to-cycle
• IDT2305B-1 for Standard Drive
• IDT2305B-1H for High Drive
• No external RC network required
• Operates at 3.3V VDD
• Power down mode
• Available in SOIC package
DESCRIPTION:
The IDT2305B is a high-speed phase-lock loop (PLL) clock buffer,
designed to address high-speed clock distribution applications. The zero
delay is achieved by aligning the phase between the incoming clock and
the output clock, operable within the range of 10 to 133MHz.
The IDT2305B is an 8-pin version of the IDT2309B. IDT2305B accepts
one reference input, and drives out five low skew clocks. The -1H version
of this device operates, up to 133MHz frequency and has a higher drive
than the -1 device. All parts have on-chip PLLs which lock to an input clock
on the REF pin. The PLL feedback is on-chip and is obtained from the
CLKOUT pad. In the absence of an input clock, the IDT2305B enters power
down. In this mode, the device will draw less than 25μA, the outputs are
tri-stated, and the PLL is not running, resulting in a significant reduction of
power.
The IDT2305B is characterized for both Industrial and Commercial
operation.
FUNCTIONAL BLOCK DIAGRAM
REF 1
PLL
Control
Logic
8
CLKOUT
3 CLK1
2 CLK2
5 CLK3
7
CLK4
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL
c 2007 Integrated Device Technology, Inc.
TEMPERATURE
1
RANGES
SEPTEMBER 2007
DSC 6994/4
1 page IDT2305B
3.3V ZERO DELAY CLOCK BUFFER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS (2305B-1) - INDUSTRIAL(1,2)
Symbol
Parameter
Conditions
Min.
t1 Output Frequency
10pF Load
10
30pF Load
10
Duty Cycle = t2 ÷ t1
Measured at 1.4V, FOUT = 66.66MHz
40
t3 Rise Time
Measured between 0.8V and 2V
—
t4 Fall Time
Measured between 0.8V and 2V
—
t5 Output to Output Skew
All outputs equally loaded
—
t6 Delay, REF Rising Edge to CLKOUT Rising Edge Measured at VDD/2
—
t7 Device-to-Device Skew
Measured at VDD/2 on the CLKOUT pins of devices
—
tJ Cycle-to-Cycle Jitter, pk - pk
Measured at 66.66MHz, loaded outputs
—
tLOCK PLL Lock Time
Stable power supply, valid clock presented on REF pin —
Typ. Max.
— 133
— 100
50 60
— 2.5
— 2.5
— 250
0 ±350
0 700
— 200
—1
Unit
MHz
%
ns
ns
ps
ps
ps
ps
ms
NOTES:
1. REF Input has a threshold voltage of VDD/2.
2. All parameters specified with loaded outputs.
SWITCHING CHARACTERISTICS (2305B-1H) - INDUSTRIAL(1,2)
Symbol
Parameter
Conditions
Min.
t1 Output Frequency
10pF Load
30pF Load
10
10
Duty Cycle = t2 ÷ t1
Measured at 1.4V, FOUT = 66.66MHz
40
Duty Cycle = t2 ÷ t1
Measured at 1.4V, FOUT <50MHz
45
t3 Rise Time
Measured between 0.8V and 2V
—
t4 Fall Time
Measured between 0.8V and 2V
—
t5 Output to Output Skew
All outputs equally loaded
—
t6 Delay, REF Rising Edge to CLKOUT Rising Edge Measured at VDD/2
—
t7 Device-to-Device Skew
Measured at VDD/2 on the CLKOUT pins of devices
—
t8 Output Slew Rate
Measured between 0.8V and 2V using Test Circuit #2
1
tJ Cycle-to-Cycle Jitter, pk - pk
Measured at 66.66MHz, loaded outputs
—
tLOCK PLL Lock Time
Stable power supply, valid clock presented on REF pin —
NOTES:
1. REF Input has a threshold voltage of VDD/2.
2. All parameters specified with loaded outputs.
Typ. Max.
— 133
— 100
50 60
50 55
— 1.5
— 1.5
— 250
0 ±350
0 700
——
— 200
—1
Unit
MHz
%
%
ns
ns
ps
ps
ps
V/ns
ps
ms
5
5 Page |
Páginas | Total 10 Páginas | |
PDF Descargar | [ Datasheet IDT2305B.PDF ] |
Número de pieza | Descripción | Fabricantes |
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