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ICSSSTUBF32866A fiches techniques PDF

ICS - 25-Bit Configurable Registered Buffer

Numéro de référence ICSSSTUBF32866A
Description 25-Bit Configurable Registered Buffer
Fabricant ICS 
Logo ICS 





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ICSSSTUBF32866A fiche technique
www.DataSheet4U.com
Integrated
Circuit
Systems, Inc.
ICSSSTUBF32866A
Advance Information
25-Bit Configurable Registered Buffer for DDR2
Recommended Application:
• DDR2 Memory Modules
• Provides complete DDR DIMM solution with
ICS97ULP877
• Ideal for DDR2 667, and 800
Product Features:
• 25-bit 1:1 or 14-bit 1:2 configurable registered buffer
with parity check functionality
• Supports SSTL_18 JEDEC specification on data
inputs and outputs
• Supports LVCMOS switching levels on CSR and
RESET inputs
• Low voltage operation
VDD = 1.7V to 1.9V
• Available in 96 BGA package
• Drop-in replacement for ICSSSTUA32864
• Green packages available
Functionality Truth Table
I nputs
Outp uts
RST
DCS
CSR
CK
Dn,
CK DODT, Qn
DCK E
QCS
QODT,
QCKE
HLL
LL LL
HLL
HHL H
H
L
L L or H L or H X
Q0 Q0 Q0
HLH
LL LL
HLH
HHL H
H
L
H L or H L or H X
Q0 Q0 Q0
HHL
LL HL
HHL
HHHH
H H L L or H L or H X Q0 Q0 Q0
HHH
L Q0 H L
HHH
H Q0 H H
H H H L or H L or H X Q0 Q0 Q0
L
X or X or X or X or X or
Floating Floating Floating Floating Floating
L
L
L
Pin Configuration
123456
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
96 Ball BGA
(Top View)
1240—07/17/06
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.

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