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PDF ICS889832 Data sheet ( Hoja de datos )
| Número de pieza | ICS889832 | |
| Descripción | 1-TO-4 DIFFERENTIAL-TOLVDS FANOUT BUFFER | |
| Fabricantes | IDT | |
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LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-
LVDS FANOUT BUFFER
GENERAL DESCRIPTION
The ICS889832 is a high speed 1-to-4 Differential-
ICS to-LVDS Fanout Buffer and is a member of the
HiPerClockS™ HiPerClockS™ family of high performance clock
solutions from IDT. The ICS889832 is optimized
for high speed and very low output skew, making
it suitable for use in demanding applications such as SONET,
1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel. The
internally terminated differential input and VREF_AC pin allow
other differential signal families such as LVPECL, LVDS, and
SSTL to be easily interfaced to the input with minimal use of
external components. The device also has an output enable
pin which may be useful for system test and debug purposes.
The ICS889832 is packaged in a small 3mm x 3mm 16-pin
VFQFN package which makes it ideal for use in space-
constrained applications.
ICS889832
FEATURES
• Four differential LVDS outputs
• IN, nIN pair can accept the following differential input levels:
LVPECL, LVDS, SSTL
•
50Ω
internal
input
termination
to
V
T
• Output frequency: >2GHz
• Output skew: 25ps (maximum)
• Part-to-part skew: 200ps (maximum)
• Additive phase jitter, RMS: <0.2ps (typical)
• Propagation delay: 510ps (maximum)
• 2.5V operating supply
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
BLOCK DIAGRAM
IN
50Ω
VT
50Ω
nIN
VREF_AC
EN
DQ
PIN ASSIGNMENT
16 15 14 13
Q0
Q1 1
12 IN
nQ0
nQ1 2
11 VT
Q2 3
10 VREF_AC
Q1
nQ2 4
9 nIN
5678
nQ1
Q2 ICS889832
nQ2 16-Lead VFQFN
3mm x 3mm x 0.95 package body
Q3 K Package
Top View
nQ3
IDT™ / ICS™ LVDS FANOUT BUFFER
1 ICS889832AK REV A SEPTEMBER 19, 2006
1 page  
ICS889832
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
TABLE 4D. LVDS DC CHARACTERISTICS, VDD = 2.5V ± 5%; TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
V
OD
∆ VOD
VOS
∆
V
OS
Differential Output Voltage
VOD Magnitude Change
Offset Voltage
VOS Magnitude Change
Minimum
0.3
1
Typical
0.4
1.25
Maximum
0.5
50
1.5
50
Units
mV
mV
V
mV
TABLE 5. AC CHARACTERISTICS, VDD = 2.5V ± 5%; TA = -40°C TO 85°C
Symbol Parameter
Condition
Minimum Typical Maximum
fMAX
tPD
tsk(o)
Maximum Output Frequency
Propagation Delay; (Differential);
NOTE 1
Output Skew; NOTE 2, 4
>2
275 390
510
25
tsk(pp)
tjit
Part-to-Part Skew; NOTE 3, 4
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section
Integration Range:
12kHz - 20MHz
<0.2
200
tR/tF Output Rise/Fall Time
20% to 80%
70 150
tS Clock Enable Setup Time EN to IN, nIN
300
tH Clock Enable Hold Time EN to IN, nIN
300
All parameters are measured at ≤ 1GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
235
Units
GHz
ps
ps
ps
ps
ps
ps
ps
IDT™ / ICS™ LVDS FANOUT BUFFER
5 ICS889832AK REV A SEPTEMBER 19, 2006
5 Page 
ICS889832
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS889832.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS889832 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V = 2.5V + 5% = 2.625V, which gives worst case results.
DD
• Power_ = V * I = 2.625V * 120mA = 315mW
MAX
DD_MAX
DD_MAX
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T = Ambient Temperature
A
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air
flow of and a multi-layer board, the appropriate value is 51.5°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.315W * 51.5°C/W = 101.2°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and
the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θ FOR 16-PIN VFQFN, FORCED CONVECTION
JA
θ vs. 0 Air Flow (Linear Feet per Minute)
JA
Multi-Layer PCB, JEDEC Standard Test Boards
0
51.5°C/W
IDT™ / ICS™ LVDS FANOUT BUFFER
11 ICS889832AK REV A SEPTEMBER 19, 2006
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet ICS889832.PDF ] | |
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