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PDF ICS8442I Data sheet ( Hoja de datos )
| Número de pieza | ICS8442I | |
| Descripción | CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER | |
| Fabricantes | ICS | |
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Integrated
Circuit
Systems, Inc.
ICS8442I
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL
LVDS FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
ICS
HiPerClockS™
The ICS8442I is a general purpose, dual output
Crystal-to-Differential LVDS High Frequency
Synthesizer and a member of the HiPerClockS™
family of High Performance Clock Solutions from
• Dual differential LVDS outputs
• Selectable crystal oscillator interface or
LVCMOS/LVTTL TEST_CLK
ICS. The ICS8442I has a selectable TEST_CLK • Output frequency range: 31.25MHz to 700MHz
or crystal input. The TEST_CLK input accepts LVCMOS or
LVTTL input levels and translates them to LVDS levels. The • Crystal input frequency range: 10MHz to 25MHz
VCO operates at a frequency range of 250MHz to 700MHz. • VCO range: 250MHz to 700MHz
The VCO frequency is programmed in steps equal to the value
of the input reference or crystal frequency. The VCO and output • Parallel or serial interface for programming counter
frequency can be programmed using the serial or parallel
and output dividers
interface to the configuration logic. The low phase noise • RMS period jitter: 3.5ps (typical)
characteristics of the ICS8442I makes it an ideal clock source
for Gigabit Ethernet and Sonet applications.
• Cycle-to-cycle jitter: 18ps (typical)
• 3.3V supply voltage
• -40°C to 85°C ambient operating temperature
BLOCK DIAGRAM
VCO_SEL
XTAL_SEL
TEST_CLK
XTAL_IN
XTAL_OUT
OSC
0
1
MR
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M0:M8
N0:N1
PLL
PHASE DETECTOR
÷1
VCO
÷2
0 ÷4
÷M 1 ÷8
CONFIGURATION
INTERFACE
LOGIC
PIN ASSIGNMENT
FOUT0
nFOUT0
FOUT1
nFOUT1
M5
M6
M7
M8
N0
N1
nc
GND
32 31 30 29 28 27 26 25
1 24
2 23
3 22
4 ICS8442I 21
5 20
6 19
7 18
8 17
9 10 11 12 13 14 15 16
XTAL_OUT
TEST_CLK
XTAL_SEL
VDDA
S_LOAD
S_DATA
S_CLOCK
MR
TEST
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
8442AYI
www.icst.com/products/hiperclocks.html
1
REV. C MAY 10, 2005
1 page  
Integrated
Circuit
Systems, Inc.
ICS8442I
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL
LVDS FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
Inputs, VI
Outputs, VO
Package Thermal Impedance, θJA
Storage Temperature, TSTG
4.6V
-0.5V to VDD + 0.5 V
-0.5V to VDD + 0.5V
47.9°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VDD
VDDA
IDD
IDDA
Core Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
3.135
3.3
3.465
V
3.135
3.3
3.465
V
155 mA
20 mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions Minimum Typical
M0-M8, N0, N1, MR, nP_LOAD,
VIH
Input
S_CLOCK, S_DATA, S_LOAD,
High Voltage XTAL_SEL, VCO_SEL
TEST_CLK
2
2
M0-M8, N0, N1, MR, nP_LOAD,
VIL
Input
S_CLOCK, S_DATA, S_LOAD,
Low Voltage XTAL_SEL, VCO_SEL
TEST_CLK
-0.3
-0.3
M0-M4, M6-M8, N0, N1, MR,
IIH
Input
nP_LOAD, S_CLOCK, S_DATA, VDD = VIN = 3.465V
High Current S_LOAD,
M5, XTAL_SEL, VCO_SEL
VDD = VIN = 3.465V
M0-M4, M6-M8, N0, N1, MR,
nP_LOAD, S_CLOCK, S_DATA,
VDD = 3.465V,
-5
IIL
Input
S_LOAD,
Low Current
M5, XTAL_SEL, VCO_SEL
VIN = 0V
VDD = 3.465V,
-150
VIN = 0V
VOH
Output
High Voltage
TEST; NOTE 1
2.6
VOL
Output
Low Voltage
TEST; NOTE 1
NOTE 1: Outputs terminated with 50Ω to VDD/2. See Parameter Measurement Information section,
"3.3V Output Load Test Circuit".
TABLE 4C. LVDS DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical
Maximum
VDD + 0.3
VDD + 0.3
0.8
1.3
150
5
0.5
Maximum
Units
V
V
V
V
µA
µA
V
V
Units
VOD
Δ VOD
VOS
Δ
V
OS
Differential Output Voltage
VOD Magnitude Change
Offset Voltage
VOS Magnitude Change
250
1.125
450
1.4
600 mV
50 mV
1.6 V
50 mV
8442AYI
www.icst.com/products/hiperclocks.html
REV. C MAY 10, 2005
5
5 Page 
Integrated
Circuit
Systems, Inc.
ICS8442I
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL
LVDS FREQUENCY SYNTHESIZER
The following component footprints are used in this layout
example: All the resistors and capacitors are size 0603.
POWER AND GROUNDING
Place the decoupling capacitors C14 and C15 as close as pos-
sible to the power pins. If space allows, placing the decoupling
capacitor at the component side is preferred. This can reduce
unwanted inductance between the decoupling capacitor and the
power pin generated by the via.
Maximize the pad size of the power (ground) at the decoupling
capacitor. Maximize the number of vias between power (ground)
and the pads.This can reduce the inductance between the power
(ground) plane and the component power (ground) pins.
If VCCA shares the same power supply with VCC, insert the RC
filter R7, C11, and C16 in between. Place this RC filter as close
to the V as possible.
CCA
CLOCK TRACES AND TERMINATION
The component placements, locations and orientations should
be arranged to achieve the best clock signal quality. Poor clock
signal quality can degrade the system performance or cause
system failure. In the synchronous high-speed digital system,
the clock signal is less tolerable to poor signal quality than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The trace shape and the trace
delay might be restricted by the available space on the board and
the component location.While routing the traces, the clock signal
traces should be routed first and should be locked prior to routing
other signal traces.
• The traces with 50Ω transmission lines TL1 and TL2 at
FOUT and nFOUT should have equal delay and run ad-
jacent to each other.Avoid sharp angles on the clock trace.
Sharp angle turns cause the characteristic impedance to
change on the transmission lines.
• Keep the clock traces on the same layer.Whenever pos-
sible, avoid any vias on the clock traces. Any via on the
trace can affect the trace characteristic impedance and
hence degrade signal quality.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow more space between the clock trace
and the other signal trace.
• Make sure no other signal trace is routed between the
clock trace pair.
The matching termination resistors R1 and R2 should be located
as close to the receiver input pins as possible. Other termination
scheme can also be used but is not shown in this example.
CRYSTAL
The crystal X1 should be located as close as possible to the pins
24 (XTAL_OUT) and 25 (XTAL_IN).The trace length between the
X1 and U1 should be kept to a minimum to avoid unwanted para-
sitic inductance and capacitance. Other signal traces should not
be routed near the crystal traces.
C1
U1
PIN 1
C2
X1
C11
R7
C16
VDDA
GND
VDD
VIA
8442AYI
C14
C15
TL1
TL1N
Close to the input
pins of the
receiver
R1
For FOUT0/n FOUT0
output TL1, TL1N are
50 Ohm traces and
equal length
Same requirement fo
FOUT1/nFOUT1
FIGURE 5B. PCB BOARD LAYOUT FOR ICS8442I
www.icst.com/products/hiperclocks.html
11
REV. C MAY 10, 2005
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet ICS8442I.PDF ] | |
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