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PDF ICS844004I-01 Data sheet ( Hoja de datos )
| Número de pieza | ICS844004I-01 | |
| Descripción | CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER | |
| Fabricantes | ICS | |
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www.DataSheet4U.com
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS844004I-01
FEMTOCLOCKS™CRYSTAL-TO-
LVDS FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
The ICS844004I-01 is a 4 output LVDS Synthesizer
ICS optimized to generate Ethernet reference clock
HiPerClockS™ frequencies and is a member of the HiPerClocksTM
family of high performance clock solutions from
ICS. Using a 25MHz 18pF parallel resonant crystal,
the following frequencies can be generated based on the 2
frequency select pins (F_SEL[1:0]): 156.25MHz, 125MHz and
62.5MHz. The ICS844004I-01 uses ICS’ 3rd generation
low phase noise VCO technology and can achieve <1ps
typical rms phase jitter, easily meeting Ethernet jitter
requirements. The ICS844004I-01 is packaged in a small 24-
pin TSSOP package.
FEATURES
• Four LVDS outputs
• Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
• Supports the following output frequencies: 156.25MHz,
125MHz, 62.5MHz
• VCO range: 560MHz - 680MHz
• RMS phase jitter @ 156.25MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.41ps (typical)
• Full 3.3V or 2.5V supply modes
• -40°C to 85°C ambient operating temperature
FREQUENCY SELECT FUNCTION TABLE
F_SEL1
0
F_SEL0
0
M Divider
Value
25
N Divider
Value
4
M/N Divider
Value
6.25
Output
Frequency
(25MHz Ref.)
156.5
0 1 25
5
5
125
1 0 25 10
2.5
62.5
1 1 25
Not Used
Not Used
BLOCK DIAGRAM
F_SEL[1:0] Pulldown
nPLL_SEL Pulldown
TEST_CLK Pulldown
25MHz
XTAL_IN
OSC
XTAL_OUT
nXTAL_SEL Pulldown
1
0
MR Pulldown
2
Phase
Detector
VCO
625MHz
(w/25MHz
Reference)
M = 25 (fixed)
1
0
F_SEL[1:0]
0 0 ÷4
0 1 ÷5
1 0 ÷10
1 1 not used
PIN ASSIGNMENT
nQ1
Q1
VDDo
Q0
nQ0
MR
nPLL_SEL
nc
VDDA
F_SEL0
VDD
F_SEL1
1
2
3
4
5
6
7
8
9
10
11
12
24 nQ2
23 Q2
22 VDDO
21 Q3
20 nQ3
19 GND
18 VDD
17 nXTAL_SEL
16 TEST_CLK
15 GND
14 XTAL_IN
13 XTAL_OUT
ICS844004I-01
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Q0 Top View
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
844004AGI-01
www.icst.com/products/hiperclocks.html
REV. A JUNE 15, 2005
1
1 page  
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS844004I-01
FEMTOCLOCKS™CRYSTAL-TO-
LVDS FREQUENCY SYNTHESIZER
TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical
F_SEL[1:0] = 00
156.5
fOUT Output Frequency
F_SEL[1:0] = 01
F_SEL[1:0] = 10
125
62.5
tsk(o) Output Skew; NOTE 1, 2
TBD
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 3
156.25MHz, (1.875MHz - 20MHz)
125MHz, (1.875MHz - 20MHz)
62.5MHz, (1.875MHz - 20MHz)
0.41
0.44
0.47
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
450
50
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
Maximum
Units
MHz
MHz
MHz
ps
ps
ps
ps
ps
%
TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
F_SEL[1:0] = 00
156.5
MHz
f Output Frequency
OUT
F_SEL[1:0] = 01
F_SEL[1:0] = 10
125
62.5
MHz
MHz
tsk(o) Output Skew; NOTE 1, 2
TBD
ps
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 3
156.25MHz, (1.875MHz - 20MHz)
125MHz, (1.875MHz - 20MHz)
62.5MHz, (1.875MHz - 20MHz)
0.41
0.44
0.47
ps
ps
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
480
50
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
ps
%
844004AGI-01
www.icst.com/products/hiperclocks.html
5
REV. A JUNE 15, 2005
5 Page 
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS844004I-01
FEMTOCLOCKS™CRYSTAL-TO-
LVDS FREQUENCY SYNTHESIZER
PACKAGE OUTLINE - G SUFFIX FOR 24 LEAD TSSOP
844004AGI-01
TABLE 7. PACKAGE DIMENSIONS
SYMBOL
Millimeters
Minimum
Maximum
N 24
A -- 1.20
A1 0.05 0.15
A2 0.80 1.05
b 0.19 0.30
c 0.09 0.20
D 7.70 7.90
E 6.40 BASIC
E1 4.30 4.50
e 0.65 BASIC
L 0.45 0.75
α 0° 8°
aaa -- 0.10
Reference Document: JEDEC Publication 95, MO-153
www.icst.com/products/hiperclocks.html
11
REV. A JUNE 15, 2005
11 Page | ||
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