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PDF ICS844004I Data sheet ( Hoja de datos )
| Número de pieza | ICS844004I | |
| Descripción | CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER | |
| Fabricantes | ICS | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS844004I
FEMTOCLOCKS™CRYSTAL-TO-
LVDS FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
The ICS844004I is a 4 output LVDS Synthesizer
ICS optimized to generate Fibre Channel reference
HiPerClockS™ clock frequencies and is a member of the
HiPerClocksTM family of high performance clock
solutions from ICS. Using a 26.5625MHz 18pF
parallel resonant crystal, the following frequencies can be
generated based on the 2 frequency select pins (F_SEL[1:0]):
212.5MHz, 187.5MHz, 159.375MHz, 156.25MHz, 106.25MHz
and 53.125MHz. The ICS844004I uses ICS’ 3rd generation
low phase noise VCO technology and can achieve <1ps
typical rms phase jitter, easily meeting Fibre Channel jitter
requirements. The ICS844004I is packaged in a small 24-pin
TSSOP package.
FEATURES
• Four LVDS outputs
• Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
• Supports the following output frequencies: 212.5MHz,
187.5MHz, 159.375MHz, 156.25MHz, 106.25MHz, 53.125MHz
• VCO range: 560MHz - 680MHz
• RMS phase jitter @ 212.5MHz, using a 26.5625MHz crystal
(637KHz - 10MHz): 0.65ps (typical)
• Full 3.3V or 2.5V supply modes
• -40°C to 85°C ambient operating temperature
FREQUENCY SELECT FUNCTION TABLE
Input
Frequency
(MHz)
26.5625
F_SEL1
Inputs
F_SEL0
M Divider
Value
N Divider
Value
M/N Divider
Value
Output
Frequency
(MHz)
0 0 24
3
8 212.5
26.5625
0
1
24
4
6 159.375
26.5625
1
0
24
6
4 106.25
26.5625
1
1
24
12
2 53.125
26.04166
0
1
24
4
6 156.25
23.4375
0
0
24
3
8 187.5
BLOCK DIAGRAM
F_SEL[1:0] Pulldown
nPLL_SEL Pulldown
TEST_CLK Pulldown
26.5625MHz
XTAL_IN
OSC
XTAL_OUT
nXTAL_SEL Pulldown
1
0
2
Phase
Detector
VCO
637.5MHz
(w/26.5625MHz
Reference)
1
0
F_SEL[1:0]
0 0 ÷3
0 1 ÷4
1 0 ÷6
1 1 ÷12
M = 24 (fixed)
MR Pulldown
PIN ASSIGNMENT
nQ1
Q1
VDDo
Q0
nQ0
MR
nPLL_SEL
nc
VDDA
F_SEL0
VDD
F_SEL1
1
2
3
4
5
6
7
8
9
10
11
12
24 nQ2
23 Q2
2 2 VDDO
21 Q3
20 nQ3
19 GND
18 nc
17 nXTAL_SEL
16 TEST_CLK
15 GND
14 XTAL_IN
13 XTAL_OUT
ICS844004I
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Q0 Top View
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
844004AGI
www.icst.com/products/hiperclocks.html
REV. A JUNE 15, 2005
1
1 page  
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS844004I
FEMTOCLOCKS™CRYSTAL-TO-
LVDS FREQUENCY SYNTHESIZER
TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical
F_SEL[1:0] = 00
186.67
fOUT Output Frequency
F_SEL[1:0] = 01
F_SEL[1:0] = 10
140
93.33
F_SEL[1:0] = 11
46.67
tsk(o) Output Skew; NOTE 1, 2
TBD
212.5MHz, (637kHz - 10MHz)
0.65
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 3
159.375MHz, (637kHz - 10MHz)
156.25MHz, (637kHz - 10MHz))
106.25MHz, (637kHz -10MHz)
0.61
0.74
0.64
53.125MHz, (637kHz - 10MHz)
0.80
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
400
50
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
Maximum
226.66
170
113.33
56.66
Units
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
ps
%
TABLE 5B.
AC
CHARACTERISTICS,
V
DD
=
V
DDA
=
V
DDO
= 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter
fOUT Output Frequency
tsk(o) Output Skew; NOTE 1, 2
Test Conditions
F_SEL[1:0] = 00
F_SEL[1:0] = 01
F_SEL[1:0] = 10
F_SEL[1:0] = 11
212.5MHz, (637kHz - 10MHz)
Minimum
186.67
140
93.33
46.67
Typical
TBD
0.65
Maximum
226.66
170
113.33
56.66
Units
MHz
MHz
MHz
MHz
ps
ps
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 3
159.375MHz, (637kHz - 10MHz)
156.25MHz, (637kHz - 10MHz))
106.25MHz, (637kHz -10MHz)
0.61
0.74
0.64
ps
ps
ps
53.125MHz, (637kHz - 10MHz)
0.80
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
430
50
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
ps
ps
%
844004AGI
www.icst.com/products/hiperclocks.html
5
REV. A JUNE 15, 2005
5 Page 
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS844004I
FEMTOCLOCKS™CRYSTAL-TO-
LVDS FREQUENCY SYNTHESIZER
PACKAGE OUTLINE - G SUFFIX FOR 24 LEAD TSSOP
844004AGI
TABLE 7. PACKAGE DIMENSIONS
SYMBOL
Millimeters
Minimum
Maximum
N 24
A -- 1.20
A1 0.05 0.15
A2 0.80 1.05
b 0.19 0.30
c 0.09 0.20
D 7.70 7.90
E 6.40 BASIC
E1 4.30 4.50
e 0.65 BASIC
L 0.45 0.75
α 0° 8°
aaa -- 0.10
Reference Document: JEDEC Publication 95, MO-153
www.icst.com/products/hiperclocks.html
11
REV. A JUNE 15, 2005
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet ICS844004I.PDF ] | |
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