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PDF ICS844001-21 Data sheet ( Hoja de datos )
| Número de pieza | ICS844001-21 | |
| Descripción | CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER | |
| Fabricantes | ICS | |
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PRELIMINARY
FEMTOCLOCKS™ CRYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
The ICS844001-21 is a a highly versatile, low
ICS phase noise LVDS Synthesizer which can generate
HiPerClockS™ l o w j i t t e r r e fe r e n c e c l o ck s fo r a va r i e t y o f
communications applications and is a member of
the HiPerClocksTM family of high performance clock
solutions from IDT. The dual crystal interface allows the
synthesizer to support up to two communications standards in
a given application (i.e. 1GB Ethernet with a 25MHz crystal
and 1Gb Fibre Channel using a 25.5625MHz crystal). The rms
phase jitter performance is typically less than 1ps, thus making
the device acceptable for use in demanding applications such
as OC48 SONET and 10Gb Ethernet. The ICS844001-21 is
packaged in a small 24-pin TSSOP package.
ICS844001-21
FEATURES
• One differential LVDS output pair and
one LVCMOS reference output
• Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
• VCO range: 560MHz - 700MHz
• Supports the following applications:
SONET, Ethernet, Fibre Channel, Serial ATA, and HDTV
• RMS phase jitter @ 622.08MHz (12kHz - 20MHz):
0.92ps (typical)
• Full 3.3V supply mode
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
BLOCK DIAGRAM
N2:N0
3
SEL0 Pulldown
SEL1 Pulldown
XTAL_IN0
XTAL_OUT0
OSC
XTAL_IN1
XTAL_OUT1
OSC
REF_CLK Pulldown
00
01
10
11
MR Pulldown
M2:M0
3
REF_OE Pulldown
11
Phase
Detector
VCO
M
000 ÷18
001 ÷22
010 ÷24
011 ÷25
100 ÷32 (default)
101 ÷40
110 ÷40
111 ÷40
10
01
00
N
000 ÷1
001 ÷2
010 ÷3
011 ÷4 (default)
100 ÷5
101 ÷6
110 ÷8
111 ÷10
PIN ASSIGNMENT
VDDO_CMOS
N0
N1
N2
VDDO_LVDS
Q0
Q nQ0
nQ GND
VDDA
VDD
XTAL_OUT1
XTAL_IN1
1
2
3
4
5
6
7
8
9
10
11
12
24 REF_OUT
23 GND
22 REF_OE
21 M2
20 M1
19 M0
18 MR
17 SEL1
16 SEL0
15 REF_CLK
14 XTAL_IN0
13 XTAL_OUT0
ICS844001-21
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Top View
REF_OUT
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™ INSERT PRODUCT NAME
1 ICS844001AG-21 REV. A SEPTEMBER 14, 2007
1 page  
ICS844001-21
FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
PRELIMINARY
TABLE 4C. LVDS DC CHARACTERISTICS, VDD = VDDO_LVDS = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
VOD
Δ VOD
VOS
Δ VOS
Differential Output Voltage
VOD Magnitude Change
Offset Voltage
V Magnitude Change
OS
Typical
400
50
1.5
50
Maximum
Units
mV
mV
V
mV
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
NOTE: Characterized using an 18pF parallel resonant crystal.
Minimum Typical Maximum
Fundamental
12 40
50
7
1
Units
MHz
MHz
Ω
pF
mW
TABLE 6.
AC
CHARACTERISTICS,
V
DD
=
V
DDO_LVDS
=V
DDO_CMOS
= 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
f
OUT
tPD
tjit(Ø)
tR / tF
Output Frequency
Propagation Delay, REF_CLK to
NOTE 1
REF_OUT
RMS Phase Jitter, (Random);
NOTE 2, 3
Output
Rise/Fall Time
Q, nQ
REF_OUT
622.08MHz (12kHz - 20MHz)
20% to 80%
20% to 80%
56
Q, nQ
odc Output Duty Cycle
REF_OUT
NOTE 1: Measured from the VDD/2 of the input to VDDO_CMOS/2 of the output.
NOTE 2: Phase jitter measured using a 25MHz quartz crystal.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
Typical
2.95
0.92
300
300
50
50
Maximum Units
700 MHz
ns
ps
ps
ps
%
%
IDT™ / ICS™ INSERT PRODUCT NAME
5 ICS844001AG-21 REV. A SEPTEMBER 14, 2007
5 Page 
ICS844001-21
FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
PRELIMINARY
SCHEMATIC EXAMPLE
Figure 5 shows an example of ICS844001-21 application
schematic. In this example, the device is operated at V = 3.3V.
DD
The 18pF parallel resonant 25MHz crystal is used. The C1 = 22pF
and C2 = 22pF are recommended for frequency accuracy. For
different board layout, the C1 and C2 may be slightly adjusted for
optimizing frequency accuracy. One example of LVDS and one
example of LVCMOS terminations are shown in this schematic.
The decoupling capacitors should be located as close as possible
to the power pin.
FIGURE 5. ICS844001-21 SCHEMATIC LAYOUT
IDT™ / ICS™ INSERT PRODUCT NAME
11 ICS844001AG-21 REV. A SEPTEMBER 14, 2007
11 Page | ||
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