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PDF 89HPES8T5A Data sheet ( Hoja de datos )
| Número de pieza | 89HPES8T5A | |
| Descripción | 8-Lane 5-Port PCI Express Switch | |
| Fabricantes | IDT | |
| Logotipo |  |
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8-Lane 5-Port
PCI Express® Switch
®
89HPES8T5A
Data Sheet
Advance Information*
Device Overview
The 89HPES8T5A is a member of IDT’s PRECISE™ family of PCI
Express switching solutions. The PES8T5A is an 8-lane, 5-port periph-
eral chip that performs PCI Express Base switching. It provides connec-
tivity and switching functions between a PCI Express upstream port and
up to four downstream ports and supports switching between down-
stream ports.
Features
◆ High Performance PCI Express Switch
– Eight 2.5Gbps PCI Express lanes
– Five switch ports
– Upstream port is x4
– Downstream ports are x1
– Low-latency cut-through switch architecture
– Support for Max Payload Sizes up to 256 bytes
– One virtual channel
– Eight traffic classes
– PCI Express Base Specification Revision 1.1 compliant
◆ Flexible Architecture with Numerous Configuration Options
– Automatic lane reversal on all ports
– Automatic polarity inversion on all lanes
– Ability to load device configuration from serial EEPROM
◆ Legacy Support
– PCI compatible INTx emulation
– Bus locking
◆ Highly Integrated Solution
– Requires no external components
– Incorporates on-chip internal memory for packet buffering and
queueing
– Integrates eight 2.5 Gbps embedded SerDes with 8B/10B
encoder/decoder (no separate transceivers needed)
◆ Reliability, Availability, and Serviceability (RAS) Features
– Internal end-to-end parity protection on all TLPs ensures data
integrity even in systems that do not implement end-to-end
CRC (ECRC)
– Supports ECRC and Advanced Error Reporting
– Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O
– Compatible with Hot-Plug I/O expanders used on PC mother-
boards
◆ Power Management
– Utilizes advanced low-power design techniques to achieve low
typical power consumption
– Supports PCI Power Management Interface specification (PCI-
PM 1.2)
– Unused SerDes are disabled.
– Supports Advanced Configuration and Power Interface Speci-
fication, Revision 2.0 (ACPI) supporting active link state
◆ Testability and Debug Features
– Built in Pseudo-Random Bit Stream (PRBS) generator
– Numerous SerDes test modes
– Ability to read and write any internal register via the SMBus
– Ability to bypass link training and force any link into any mode
– Provides statistics and performance counters
Block Diagram
Frame Buffer
5-Port Switch Core / 8 PCI Express Lanes
Route Table
Port
Arbitration
Scheduler
Transaction Layer
Data Link Layer
Mux / Demux
Phy
Logical
Layer
SerDes
Transaction Layer
Data Link Layer
Mux / Demux
Phy
Logical
Layer
SerDes
Transaction Layer
Data Link Layer
Mux / Demux
Phy
Logical
Layer
SerDes
Transaction Layer
Data Link Layer
Mux / Demux
Phy
Logical
Layer
SerDes
Transaction Layer
Data Link Layer
Mux / Demux
Phy
Logical
Layer
SerDes
(Port 0)
(Port 2)
(Port 3)
(Port 4)
Figure 1 Internal Block Diagram
© 2007 Integrated Device Technology, Inc.
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
1 of 29
*Notice: The information in this document is subject to change without notice
(Port 5)
September 7, 2007
1 page  
IDT 89HPES8T5A Data Sheet
Signal
Type
Name/Description
MSMBADDR[4:1]
I Master SMBus Address. These pins determine the SMBus address of the
serial EEPROM from which configuration information is loaded.
MSMBCLK
I/O Master SMBus Clock. This bidirectional signal is used to synchronize
transfers on the master SMBus.
MSMBDAT
I/O Master SMBus Data. This bidirectional signal is used for data on the mas-
ter SMBus.
SSMBADDR[5,3:1] I Slave SMBus Address. These pins determine the SMBus address to
which the slave SMBus interface responds.
SSMBCLK
I/O Slave SMBus Clock. This bidirectional signal is used to synchronize trans-
fers on the slave SMBus.
SSMBDAT
I/O Slave SMBus Data. This bidirectional signal is used for data on the slave
SMBus.
Table 3 SMBus Interface Pins
Signal
GPIO[0]
GPIO[1]
GPIO[2]
GPIO[3]
GPIO[4]
GPIO[5]
GPIO[6]
Type
Name/Description
I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P2RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 2
I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P4RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 4
I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN0
Alternate function pin type: Input
Alternate function: I/O Expander interrupt 0 input
I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN1
Alternate function pin type: Input
Alternate function: I/O Expander interrupt 1 input
I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN2
Alternate function pin type: Input
Alternate function: I/O Expander interrupt 2 input
I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Table 4 General Purpose I/O Pins (Part 1 of 2)
5 of 29
September 7, 2007
5 Page 
IDT 89HPES8T5A Data Sheet
System Clock Parameters
Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 13 and 14.
Parameter
Description
Min
PEREFCLK
RefclkFREQ
RefclkDC2
TR, TF
VSW
Tjitter
Input reference clock frequency range
Duty cycle of input clock
Rise/Fall time of input clocks
Differential input voltage swing4
Input clock jitter (cycle-to-cycle)
100
40
0.6
Table 9 Input Clock Requirements
1. The input clock frequency will be either 100 or 125 MHz depending on signal REFCLKM.
2. ClkIn must be AC coupled. Use 0.01 — 0.1 µF ceramic capacitors.
3. RCUI (Reference Clock Unit Interval) refers to the reference clock period.
4. AC coupling required.
Typical
Max
1251
50 60
0.2*RCUI
1.6
125
Unit
MHz
%
RCUI3
V
ps
AC Timing Characteristics
Parameter
PCIe Transmit
TTX-RISE, TTX-FALL
UI
TTX-MAX-JITTER
TTX-EYE
TTX-EYE-MEDIAN-to-
MAX-JITTER
LTLAT-10
LTLAT-20
TTX-SKEW
TTX-IDLE-SET-TO-
IDLE
TEIExit
TBTEn
TRxDetectEn
TRxDetect
PCIe Receive
LRLAT-10
LRLAT-20
Description
Min Typical
Rise / Fall time of TxP, TxN outputs
Unit Interval
Transmitter Total Jitter (peak-to-peak)
Minimum Tx Eye Width (1 - TTX-MAX-JITTER)
Maximum time between the jitter median and maximum
deviation from the median
Transmitter data latency (for n=10)
Transmitter data latency (for n=20)
Transmitter data skew between any 2 lanes
Maximum time to transition to a valid electrical idle after
sending an Electrical Idle ordered set
Time to exit Electrical Idle (L0s) state into L0
Time from asserting Beacon TxEn to beacon being trans-
mitted on the lane
Pulse width of RxDetectEn input
RxDetectEn falling edge to RxDetect delay
80
399.88
0.75
9
9
9.8
400
500
4
12
30
10
1
Recover data latency for n=10
Recover data latency for n=20
28
49
Table 10 PCIe AC Timing Characteristics (Part 1 of 2)
Max
1101
400.12
0.252
0.15
11
11
1300
6
16
80
10.2
2
29
60
Units
ps
ps
UI
UI
UI
bits
bits
ps
ns
ns
ns
ns
ns
bits
bits
11 of 29
September 7, 2007
11 Page | ||
| Páginas | Total 29 Páginas | |
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