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PDF GS1561 Data sheet ( Hoja de datos )
| Número de pieza | GS1561 | |
| Descripción | (GS1560A / GS1561) HD-LINX-R II Dual-Rate Deserializer | |
| Fabricantes | Gennum Corporation | |
| Logotipo |  |
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GS1560A/GS1561 HD-LINX® II
Dual-Rate Deserializer
GS1560A/GS1561 Data Sheet
Key Features
• SMPTE 292M and SMPTE 259M-C compliant
descrambling and NRZI → NRZ decoding (with
bypass)
• DVB-ASI sync word detection and 8b/10b decoding
• auto-configuration for HD-SDI, SD-SDI and
DVB-ASI
• serial loop-through cable driver output selectable as
reclocked or non-reclocked (GS1560A only)
• dual serial digital input buffers with 2 x 1 mux
• integrated serial digital signal termination
• integrated reclocker
• automatic or manual rate selection / indication
(HD/SD)
• descrambler bypass option
• user selectable additional processing features
including:
• CRC, TRS, ANC data checksum, line number
and EDH CRC error detection and correction
• programmable ANC data detection
• illegal code remapping
• internal flywheel for noise immune H, V, F
extraction
• FIFO load Pulse
• 20-bit / 10-bit CMOS parallel output data bus
• 148.5MHz / 74.25MHz / 27MHz / 13.5MHz parallel
digital output
• automatic standards detection and indication
• Pb-free and RoHS Compliant
• 1.8V core power supply and 3.3V charge pump
power supply
• 3.3V digital I/O supply
• JTAG test interface
• small footprint compatible with GS9060, GS1532,
and GS9062
Applications
• SMPTE 292M Serial Digital Interfaces
• SMPTE 259M-C Serial Digital Interfaces
• DVB-ASI Serial Digital Interfaces
Description
The GS1560A/GS1561 is a reclocking deserializer.
When used in conjunction with the GS1524 Automatic
Cable Equalizer and the GO1525 Voltage Controlled
Oscillator, a receive solution can be realized for HD-SD,
SD-SDI and DVB-ASI applications.
In addition to reclocking and deserializing the input data
stream, the GS1560A/GS1561 performs NRZI-to-NRZ
decoding, descrambling as per SMPTE 259M-C/292M,
and word alignment when operating in SMPTE mode.
When operating in DVB-ASI mode, the device will word
align the data to K28.5 sync characters and 8b/10b
decode the received stream.
Two serial digital input buffers are provided with a 2x1
multiplexer to allow the device to select from one of two
serial digital input signals.
The integrated reclocker features a very wide Input
Jitter Tolerance of ±0.3 UI (total 0.6 UI), a rapid
asynchronous lock time, and full compliance with
DVB-ASI data streams.
The GS1560A includes an integrated cable driver is for
serial input loop-through applications. It can be selected
to output either buffered or reclocked data. The cable
driver also features an output mute on loss of signal,
high impedance mode, adjustable signal swing, and
automatic dual slew-rate selection depending on
HD/SD operational requirements.
The GS1560A/GS1561 also includes a range of data
processing functions such as error detection and
correction, automatic standards detection, and EDH
support. The device can also detect and extract SMPTE
352M payload identifier packets and independently
identify the received video standard. This information is
read from internal registers via the host interface port.
Line-based CRC errors, line number errors, TRS errors,
EDH CRC errors and ancillary data checksum errors
can all be detected.
Finally, the device can correct detected errors and
insert new TRS ID words, line-based CRC words,
ancillary data checksum words, EDH CRC words, and
line numbers. Illegal code re-mapping is also available.
All processing functions may be individually enabled or
disabled via host interface control.
The GS1560A/GS1561 is Pb-free and the
encapsulation compound does not contain halogenated
flame retardant.
This component and all homogeneous subcomponents
are RoHS compliant.
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1 page  
GS1560A/GS1561 Data Sheet
3.8.1 Transport Packet Format ....................................................................45
3.8.2 DVB-ASI 8b/10b Decoding and Word Alignment................................45
3.8.3 Status Signal Outputs .........................................................................46
3.9 Data Through Mode ......................................................................................46
3.10 Additional Processing Functions.................................................................46
3.10.1 FIFO Load Pulse...............................................................................47
3.10.2 Ancillary Data Detection and Indication ............................................48
3.10.3 SMPTE 352M Payload Identifier.......................................................52
3.10.4 Automatic Video Standard and Data Format Detection ....................52
3.10.5 Error Detection and Indication ..........................................................56
3.10.6 Error Correction and Insertion ..........................................................61
3.10.7 EDH Flag Detection ..........................................................................63
3.11 Parallel Data Outputs ..................................................................................65
3.11.1 Parallel Data Bus Buffers..................................................................65
3.11.2 Parallel Output in SMPTE Mode .......................................................66
3.11.3 Parallel Output in DVB-ASI Mode.....................................................66
3.11.4 Parallel Output in Data-Through Mode .............................................66
3.11.5 Parallel Output Clock (PCLK) ...........................................................67
3.12 GSPI Host Interface ....................................................................................68
3.12.1 Command Word Description.............................................................68
3.12.2 Data Read and Write Timing ............................................................69
3.12.3 Configuration and Status Registers ..................................................70
3.13 JTAG...........................................................................................................70
3.14 Device Power Up ........................................................................................72
3.15 Device Reset...............................................................................................72
4. Application Reference Design ................................................................................73
4.1 GS1560A Typical Application Circuit (Part A) ...............................................73
4.2 GS1560A Typical Application Circuit (Part B) ...............................................74
4.3 GS1561 Typical Application Circuit (Part A) .................................................75
4.4 GS1561 Typical Application Circuit (Part B) .................................................76
5. References & Relevant Standards.........................................................................77
6. Package & Ordering Information............................................................................78
6.1 Package Dimensions ....................................................................................78
6.2 Packaging Data.............................................................................................79
6.3 Ordering Information .....................................................................................79
7. Revision History .....................................................................................................80
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GS1560A/GS1561 Data Sheet
Table 1-1: Pin Descriptions (Continued)
Pin
Number
21
22
23, 24
25
26
Name
SDO_EN/DIS
NC
CD_GND
NC
SDO, SDO
NC
RESET_TRST
JTAG/HOST
Timing
Type Description
Non
Synchronous
–
–
–
Analog
–
Non
Synchronous
Non
Synchronous
Input
–
Power
–
Output
–
Input
Input
GS1560A
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to enable or disable the serial digital output loop-through stage.
When set LOW, the serial digital output signals SDO and SDO are
disabled and become high impedance.
When set HIGH, the serial digital output signals SDO and SDO are
enabled.
GS1561
No Connect.
GS1560A
Ground connection for the serial digital cable driver. Connect to analog
GND.
GS1561
No Connect.
GS1560A
Serial digital loop-through output signal operating at 1.485Gb/s,
1.485/1.001Gb/s, or 270Mb/s.
The slew rate of these outputs is automatically controlled to meet SMPTE
292M and 259M specifications according to the setting of the SD/HD pin.
GS1561
No Connect.
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to reset the internal operating conditions to default settings and to
reset the JTAG test sequence.
Host Mode (JTAG/HOST = LOW)
When asserted LOW, all functional blocks will be set to default conditions
and all input and output signals become high impedance, including the
serial digital outputs SDO and SDO.
Must be set HIGH for normal device operation.
NOTE: When in slave mode, reset the device after the SD/HD input has
been initially configured, and after each subsequent SD/HD data rate
change.
JTAG Test Mode (JTAG/HOST = HIGH)
When asserted LOW, all functional blocks will be set to default and the
JTAG test sequence will be held in reset.
When set HIGH, normal operation of the JTAG test sequence resumes.
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to select JTAG Test Mode or Host Interface Mode.
When set HIGH, CS_TMS, SDOUT_TDO, SDI_TDI and SCLK_TCK are
configured for JTAG boundary scan testing.
When set LOW, CS_TMS, SDOUT_TDO, SDI_TDI and SCLK_TCK are
configured as GSPI pins for normal host interface operation.
27360 - 8 September 2005
11 of 80
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet GS1561.PDF ] | |
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