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PDF GS1503 Data sheet ( Hoja de datos )
| Número de pieza | GS1503 | |
| Descripción | HD EMBEDDED AUDIO CODEC | |
| Fabricantes | Gennum Corporation | |
| Logotipo |  |
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FEATURES
• complies with SMPTE 292M and SMPTE 299M
• single chip HD embedded audio solution
• operates as an embedded audio multiplexer or
demultiplexer
• full support for 48kHz synchronous 24-bit audio
• support for 8 channels of audio per device
• cascadable architecture supports up to 16 audio channels
• integrated scrambler/descrambler and word alignment
• CRC error detection and insertion
• audio control packet insertion and extraction
• arbitrary data packet insertion and extraction
• 3.3V power supply with 5V tolerant I/O
• 144 pin LQFP package
APPLICATIONS
HD SDI Embedded Audio
ORDERING INFORMATION
PART NUMBER
PACKAGE
GS1503-CFZ
144 pin LQFP
TEMPERATURE
0°C to 70°C
GS1503
HD EMBEDDED AUDIO CODEC
DESCRIPTION
DATA SHEET
The GS1503 is a highly integrated, single chip solution for
embedding/extracting digital audio streams into and out of
high definition digital video signals. The GS1503 supports
insertion/extraction of 24-bit synchronous audio data with a
48kHz sample rate. Audio signals with different sample
rates may be converted to 48kHz by using audio sample
rate converters before or after the GS1503.
Each GS1503 supports all processing required for
embedding/extracting up to eight digital audio channels in
the horizontal ancillary data space of the video chroma
channel. Two GS1503’s can be cascaded for insertion/
extraction of up to 16 audio channels with no external glue
logic.
The GS1503 supports embedding/extracting of audio
control and arbitrary data packets in the horizontal ancillary
data space of the video luma channel. It also supports line
CRC detection and insertion.
The GS1503 supports HD video standards at 74.25MHz
and 74.25/1.001MHz rates. It has an on chip SMPTE
compliant scrambler/de-scrambler, and integrated word
alignment. Use the GS1503 with Gennum’s GS1545 or
GS1522 for two chip HD SDI receive or transmit solutions.
The GS1503 operates from a single 3.3V power supply with
5V tolerant I/O and is packaged in a 144 pin LQFP
package.
DSCBYPASS
VIN[19:0]
20
De-scrambler &
Word Alignment
VM[3:0]
4
CPUADR[8:0]
CPUDAT[7:0]
CPUCS, CPUWE,
CPURE
PKT[7:0]
PKTEN
AIN1/2
AIN3/4
AIN5/6
AIN7/8
WCINA/B
9
8 Host
Interface
3
8
4
Audio
Input
2 Interface
2
AM[1:0] MUTE
20
Video Detection &
Synchronization
ANCI Timing
Generation
Control
Packet
Mux
Arbitrary
Packet
Mux
Audio
Packet
Mux
EXTH EXTF
SCRBYPASS
20 TRS
Inserter
20 CRC Inserter &
Scrambler
20 VOUT[19:0]
VIDEO_DET
4 OPERATE
ERROR
CRC_ERR
HOST INTERFACE
HOST INTERFACE
PKTENO
MULTIPLEX MODE BLOCK DIAGRAM
Revision Date: May 2005
GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: [email protected]
www.gennum.com
Document No. 15879 - 4
1 page  
HOST INTERFACE
Mode A (CPU_SEL set HIGH)
PARAMETER
Read Cycle Time
Read Chip Select Setup Time
Read Address Setup Time
Read Data Output Delay Time
Read Data Hold Time
Write Cycle Time
Write Chip Select Setup Time
Write Address Setup Time
Write Data Setup Time
Write Data Hold Time
NUMBER
MIN
TYP
MAX
1
50 -
-
2 0- -
3
15 -
-
4 - - 15
5 0- -
6
50 -
-
7
10 -
-
8
10 -
-
9
10 -
-
10 0 - -
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CPUADR[8:0]
CPUCS
CPURE
CPUWE
CPUDAT[7:0]
Read Cycle
1
Address
2
Write Cycle
6
Address
7
3
8
Valid Data
Valid Data
4 59
Fig. 6 Host Interface Mode A Timing (CPU_SEL set HIGH)
10
5 of 83
15879 - 4
5 Page 
PIN DESCRIPTIONS (Continued)
NUMBER
SYMBOL
TYPE
79
AOUT7/8
O
85
DEC_MODE
I
87
81, 82, 83,
89, 94, 93,
92, 91, 90
103, 102,
101, 100,
99, 98, 96,
95
105
106
VCLK
CPUADR[8:0]
CPUDAT[7:0]
CPUCS
CPURE
107 CPUWE
110, 111,
112, 114,
115, 116,
118, 119,
120, 122,
123, 124,
126, 127,
128, 130,
131, 132,
134, 135
136
VIN[19:0]
CPU_SEL
137, 138
AM[1:0]
I
I
I/O
I
I
I
I
I
I
139, 140,
141, 142
143
VM[3:0]
RESET
I
I
DESCRIPTION
Audio signal output for channels 7 and 8. The AES/EBU digital audio output is bi-phase
mark encoded. In both non-AES/EBU modes, the output is not bi-phase mark encoded.
Demultiplex Mode select. Valid in Demultiplex Mode only. When set HIGH, the GS1503
requires a 48kHz word clock input at WCINA and WCINB. This word clock must be
synchronous to the word clock used to embed the audio data. The embedded audio
clock phase information in the ancillary data packet will be ignored. See Section 2-11.
Video clock signal input.
Host Interface address bus. CPUADR[8] is the MSB and CPUADR[0] is the LSB.
In Host Interface Mode B (CPU_SEL set LOW), CPUADR[1:0] are used as the Host
Interface control bus. See Table 1.
Host Interface data bus. CPUDAT[7] is the MSB and CPUDAT[0] is the LSB.
In Host Interface Mode B (CPU_SEL set LOW), CPUDAT[7:0] are used as the Host
Interface address and data bus.
Chip select for Host Interface. Active LOW.
Read enable for Host Interface. Active LOW. In Host Interface Mode B (CPU_SEL set
LOW), this input is not used.
Write enable for Host Interface. Active LOW. In Host Interface Mode B (CPU_SEL set
LOW), this input is used as the Host Interface control enable.
Parallel digital video signal input. VIN[19] is the MSB and VIN[0] is the LSB.
Host Interface mode select. When set HIGH, the GS1503 is configured for Host Interface
Mode A. When set LOW, the GS1503 is configured for Host Interface Mode B.
Audio format select. In Multiplex Mode, AM[1:0] indicates the input audio data format.
In Demultiplex Mode, AM[1:0] indicates the output audio data format. AM[1] is the MSB
and AM[0] is the LSB. See Tables 3 and 11.
Video standard select. VM[3] is the MSB and VM[0] is the LSB. See Table 2 or 10.
Device reset. Active LOW.
11 of 83
15879 - 4
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