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PDF UPD446 Data sheet ( Hoja de datos )
| Número de pieza | UPD446 | |
| Descripción | 2K x 8-BIT STATIC CMOS RAM | |
| Fabricantes | NEC | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de UPD446 (archivo pdf) en la parte inferior de esta página. Total 6 Páginas | ||
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NEe Microcomputers, Inc.
2048 x 8 BIT STATIC CMOS RAM
NEe
f'PD446
f'PD446-1
pPD446-2
~rn~[~~~ ~illrnW
DESC RIPTION
The IlPD446 is a high speed, low power, 2048 word by 8 bit static CMOS RAM
fabricated using an advanced silicon gate CMOS technology. A unique circuitry
technique makes the IlPD446 a very low operating power device which requires
no clock or refreshing to operate. Minimum standby power current is drawn by this
device when CE equals VCC independently of the other input levels.
Data retention is guaranteed at a power supply voltage as low as 2V.
The IlPD446 is packaged in a standard 24'pin dual-in-line package and is plug-in
compatible with 16K EPROMs.
FEATU RES
• Single +5V Supply
• Fully Static Operation - No Clock or Refreshing required
• TTL Compatible - All Inputs and Outputs
• Common I/O Using Three-State Output
• OE Eliminates Need for External Bus Buffers
• Max Access/Min Cycle Times Down to 120 ns
• Low Power Dissipation, 45 mA Max Activel100 IlA Max Standby/
10 IlA Max Data Retention
• Data Retention Voltage - 2V Min
• Standard 24-Pin Plastic and Ceramic Packages
• Plug-in Compatible with 16K EPROMs
II
PIN ·CONFIGURATION
2
4
5
A2 6
Al
AD S
1/01 9
1102
IlPD
446
24 VCC
23 AS
22 A9
21 WE
20 OE
19 Al0
1B CE
17 1/08
16 1107
15 1106
14 1105
13 1104
PIN NAMES
AO-Al0
'WE
Address Inputs
Write Enable
DE
CE
1/01-I/OB
VCC
Output Enable
Chip Enable
Data InputlOutput
Power (+5V)
GND
Ground
TRUTH TABLE
CE OE WE
MODE
110
ICC
H X X NOT SELECTED HZ STANDBY
L
H
H ' ' NDT SELECTED
HZ
ACTIVE
L L H READ
DOUT ACTIVE
L X L WRITE.
DIN
ACTIVE
99
1 page  
TIMING WAVEFORMS
(CONT.)
ADDRESS
WRITE CYCLE (2)
~------------twc------------~~
~----------tAw----------~
jl.PD446
I IDDUT
tDHJxxxxxx
Notes:
CD WE must be high during all address transition.
@ A write occurs during the overlap of a low CE and a low WE.
WE@ tWR is measured from the earlier of CE or gOing high to the end of write cycle.
WE@ If the CS low transition occurs simultaneously with or after the low transition,
output buffers remain in a high impedance state.
® OE is continuously low fOE - VIL).
LOW VCC DATA RETENTION
TIMING CHART
-+-_--- DATA RETENTION MODE-----t4-----tR
Vcc (5.0VI ---+--'"'\
Ce ~VIDL _________________________________________ _
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
O.BV to 2.2V
10 ns
1.5V
lTTL+l00pF
103
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet UPD446.PDF ] | |
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