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Analog Devices - 12-Bit CCD Signal Processor

Numéro de référence AD9920A
Description 12-Bit CCD Signal Processor
Fabricant Analog Devices 
Logo Analog Devices 





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AD9920A fiche technique
12-Bit CCD Signal Processor with V-Driver
and Precision Timing Generator
AD9920A
FEATURES
Integrated 19-channel V-driver
1.8 V AFETG core
24 programmable vertical clock signals
Correlated double sampler (CDS) with −3 dB, 0 dB,
+3 dB, and +6 dB gain
12-bit, 40.5 MHz analog-to-digital converter (ADC)
Black level clamp with variable level control
Complete on-chip timing generator
Precision Timing core with ~400 ps resolution
On-chip 3 V horizontal and RG drivers
General-purpose outputs (GPOs) for shutter and
system support
On-chip sync generator with external sync input
On-chip 1.8 V low dropout (LDO) regulator
105-ball, 8 mm × 8 mm CSP_BGA package
APPLICATIONS
Digital still cameras
GENERAL DESCRIPTION
The AD9920A is a highly integrated charge-coupled device (CCD)
signal processor for digital still camera applications. It includes a
complete analog front end (AFE) with analog-to-digital conversion,
combined with a full-function programmable timing generator
and 19-channel vertical driver (V-driver). The timing generator
is capable of supporting up to 24 vertical clock signals to control
advanced CCDs. The on-chip V-driver supports up to 19 channels
for use with six-field CCDs. A Precision Timing® core allows adjust-
ment of high speed clocks with approximately 400 ps resolution
at 40.5 MHz operation. The AD9920A also contains six GPOs
that can be used for shutter and system functions.
The analog front end includes black level clamping, variable
gain CDS, and a 12-bit ADC. The timing generator provides all
the necessary CCD clocks: RG, H-clocks, V-clocks, sensor gate
pulses, substrate clock, and substrate bias control.
The AD9920A is specified over an operating temperature range
of −25°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
REFT REFB
–3dB, 0dB, +3dB, +6dB
CCDIN
CDS
VGA
LDOIN
LDOOUT
LDO
REG
6dB TO 42dB
VREF
12-BIT
ADC
CLAMP
12
AD9920A
D0 TO D11
DCLK
RG
HL
H1 TO H8
V1A TO V6 (3-LEVEL)
V7 TO V16 (2-LEVEL)
SUBCK
HORIZONTAL
8 DRIVERS
XV1 TO XV24
19
VERTICAL
DRIVER
24
GPO5
GPO6
VERTICAL
TIMING
CONTROL
XSUBCK 6
INTERNAL CLOCKS
PRECISION
TIMING
GENERATOR
SYNC
GENERATOR
INTERNAL
REGISTERS
SL
SCK
SDATA
XSUBCNT
GPO1 TO GPO4,
GPO7, GPO8
Figure 1.
HD VD
CLI CLO SYNC/RST
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2009–2010 Analog Devices, Inc. All rights reserved.

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