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PDF DS3101 Data sheet ( Hoja de datos )
| Número de pieza | DS3101 | |
| Descripción | Stratum 3/3E Timing Card IC | |
| Fabricantes | Dallas Semiconductor | |
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GENERAL DESCRIPTION
When paired with an external TCXO or OCXO, the
DS3101 is a highly integrated central timing and
synchronization solution for SONET/SDH network
elements. With 14 input clocks, the device directly
accepts both line timing from a large number of line
cards and external timing from external DS1/E1 BITS
transceivers. All input clocks are continuously monitored
for frequency accuracy and activity. Any two of the input
clocks can be selected as the references for the two
core DPLLs. The T0 DPLL complies with the Stratum 3
and 3E requirements of GR-1244, GR-253, and the
requirements of G.812 Type III and G.813. From the
output of the core DPLLs, a wide variety of output clock
frequencies and frame pulses can be produced
simultaneously on the 11 output clock pins. Two
DS3101 devices can be configured in a master/slave
arrangement for timing card equipment protection.
The DS3101 registers and I/O pins are backward
compatible with Semtech’s ACS8520 and ACS8530
timing card ICs. The DS3101 is functionally equivalent
to a DS3100 without integrated BITS transceivers.
APPLICATIONS
SONET/SDH ADMs, MSPPs, and MSSPs
Digital Cross-Connects
DSLAMs
Service Provider Routers
FUNCTIONAL DIAGRAM
TIMING FROM
LINE CARDS AND
BITS/SSU RECEIVERS 14
(VARIOUS RATES)
DS3101
SONET/SDH
SYNCHRONIZATION
IC
11
TIMING TO
LINE CARDS AND
BITS/SSU TRANSMITTERS
(VARIOUS RATES)
LOCAL TCXO
OR OCXO
CONTROL STATUS
DS3101
Stratum 3/3E Timing Card IC
FEATURES
Synchronization Subsystem for Stratum 3E, 3,
4E, and 4, SMC and SEC
- Meets Requirements of GR-1244 Stratum 3/3E,
GR-253, G.812 Types I, III, and IV, and G.813
- Stratum 3E Holdover Accuracy with Suitable
External Oscillator
- Programmable Bandwidth, 0.5mHz to 70Hz
- Hitless Reference Switching on Loss of Input
- Phase Build-Out and Transient Absorption
- Locks To and Generates 125MHz for Gigabit
Synchronous Ethernet per ITU-T G.8261
14 Input Clocks
- 10 CMOS/TTL Inputs Accept 2kHz, 4kHz, and Any
Multiple of 8kHz Up to 125MHz
- Two LVDS/LVPECL/CMOS/TTL Inputs Accept
Nx8kHz Up to 125MHz Plus 155.52MHz
- Two 64kHz Composite Clock Receivers
- Continuous Input Clock Quality Monitoring
- Separate 2/4/8kHz Frame Sync Input
11 Output Clocks
- Five CMOS/TTL Outputs Drive Any Internally
Produced Clock Up to 77.76MHz
- Two LVDS Outputs Each Drive Any Internally
Produced Clock Up to 311.04MHz
- One 64kHz Composite Clock Transmitter
- One 1.544MHz/2.048MHz Output Clock
- Two Sync Pulses: 8kHz and 2kHz
- Output Clock Rates Include 2kHz, 8kHz, NxDS1,
NxDS2, DS3, NxE1, E3, 6.48MHz, 19.44MHz,
38.88 MHz, 51.84MHz, 62.5MHz, 77.76MHz,
125MHz, 155.52MHz, 311.04MHz
Internal Compensation for Master Clock
Oscillator Frequency Accuracy
Processor Interface: 8-Bit Parallel or SPI Serial
1.8V Operation with 3.3V I/O (5V Tolerant)
ORDERING INFORMATION
PART
TEMP RANGE
DS3101GN -40°C to +85°C
DS3101GN+ -40°C to +85°C
+Denotes a lead-free package.
PIN-PACKAGE
256 CSBGA (17mm)2
256 CSBGA (17mm)2
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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REV: 061307
1 page  
DS3101 Stratum 3/3E Timing Card IC
LIST OF TABLES
Table 1-1. Applicable Telecom Standards................................................................................................................... 6
Table 6-1. Input Clock Pin Descriptions .................................................................................................................... 12
Table 6-2. Output Clock Pin Descriptions.................................................................................................................. 13
Table 6-3. Global Pin Descriptions ............................................................................................................................ 14
Table 6-4. Parallel Interface Pin Descriptions ........................................................................................................... 15
Table 6-5. SPI Bus Mode Pin Descriptions ............................................................................................................... 16
Table 6-6. JTAG Interface Pin Descriptions .............................................................................................................. 16
Table 6-7. General-Purpose I/O Pin Descriptions ..................................................................................................... 16
Table 6-8. Power-Supply Pin Descriptions ................................................................................................................ 17
Table 7-1. GR-1244 Stratum 3E/3 Stability Requirements........................................................................................ 19
Table 7-2. Input Clock Capabilities ............................................................................................................................ 21
Table 7-3. Locking Frequency Modes ....................................................................................................................... 22
Table 7-4. Default Input Clock Priorities .................................................................................................................... 25
Table 7-5. Damping Factors and Peak Jitter/Wander Gain....................................................................................... 32
Table 7-6. T0 Adaptation for T4 Phase Measurement Mode .................................................................................... 36
Table 7-7. Output Clock Capabilities ......................................................................................................................... 38
Table 7-8. Digital1 and Digital2 Frequencies............................................................................................................. 41
Table 7-9. APLL Frequency to Output Frequencies (T0 and T4) .............................................................................. 42
Table 7-10. T0 APLL Frequency to T0 Path Configuration ....................................................................................... 42
Table 7-11. T4 APLL Frequency to T4 Path Configuration ....................................................................................... 43
Table 7-12. OC1 to OC7 Output Frequency Selection .............................................................................................. 44
Table 7-13. Possible Frequencies for OC1 to OC7 ................................................................................................... 44
Table 7-14. Equipment Redundancy Methodology ................................................................................................... 48
Table 7-15. Composite Clock Variations ................................................................................................................... 52
Table 7-16. GR-378 Composite Clock Interface Specification .................................................................................. 54
Table 7-17. G.703 Synchronization Interfaces Specification..................................................................................... 54
Table 7-18. Microprocessor Interface Modes ............................................................................................................ 55
Table 8-1. Top-Level Memory Map............................................................................................................................ 59
Table 8-2. Register Map ............................................................................................................................................ 60
Table 9-1. JTAG Instruction Codes ......................................................................................................................... 128
Table 9-2. JTAG ID Code ........................................................................................................................................ 129
Table 10-1. Recommended DC Operating Conditions ............................................................................................ 130
Table 10-2. DC Characteristics................................................................................................................................ 130
Table 10-3. CMOS/TTL Pins ................................................................................................................................... 131
Table 10-4. LVDS Pins ............................................................................................................................................ 131
Table 10-5. LVPECL Pins........................................................................................................................................ 132
Table 10-6. AMI Composite Clock Pins ................................................................................................................... 133
Table 10-7. Recommended External Components for Output Clock OC8.............................................................. 133
Table 10-8. Input Clock Timing................................................................................................................................ 134
Table 10-9. Input Clock to Output Clock Delay ....................................................................................................... 134
Table 10-10. Output Clock Phase Alignment, Frame Sync Alignment Mode......................................................... 134
Table 10-11. Parallel Interface Timing..................................................................................................................... 135
Table 10-12. SPI Interface Timing ........................................................................................................................... 138
Table 10-13. JTAG Interface Timing........................................................................................................................ 139
Table 11-1. Pin Assignments Sorted by Signal Name............................................................................................. 140
Table 13-1. Thermal Properties, Natural Convection .............................................................................................. 146
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5 Page 
DS3101 Stratum 3/3E Timing Card IC
5.4 Output Clock Features
11 output clocks
Five programmable-frequency CMOS/TTL output clocks drive any internally produced clock up 77.76MHz
Two programmable-frequency LVDS output clocks drive any internally produced clock up to 311.04MHz
Two sync pulses, 2kHz and 8kHz, can be disciplined by a 2kHz or 8kHz sync input
One 1.544MHz/2.048MHz output clock
One 64kHz composite clock output (AMI format)
Output clock rates include 2kHz, 8kHz, NxDS1, NxDS2, DS3, NxE1, E3, 19.44MHz, 38.88MHz, 51.84MHz,
62.5MHz, 77.76MHz, 125.0MHz, 155.52MHz, and 311.04MHz
Outputs at even divisors of 311.04MHz have less than 0.5ns peak-to-peak output jitter
5.5 Redundancy Features
Devices on redundant timing cards can be configured for master/slave operation
Clocks and frame syncs can be cross-wired between devices to ensure that slave always tracks master
Master/slave mode pin can auto-configure slave to track master with no phase build-out and wider bandwidth
Input clock priority tables can easily be kept synchronized between master and slave
5.6 Composite Clock I/O Features
Two composite clock receivers and one composite clock transmitter (all AMI format)
Compliant with Telcordia GR-378 composite clock, G.703 centralized clock, and G.703 Appendix II.1 Japanese
synchronization interfaces
Configurable for 50% or 5/8 duty cycle, 1V or 3V pulse amplitude, and 110Ω/120Ω/133Ω termination
Received signals are monitored for LOS, AMI violations, presence/absence of the 8 kHz component, and
presence/absence of the 400Hz component (for G.703 Appendix II.1 option b)
Transmitter can generate or suppress the 8kHz component and/or the 400 Hz component (for G.703 Appendix
II.1 option b)
Composite clock receiver inputs can be configured as programmable-frequency CMOS/TTL inputs if composite
clock support is not needed
5.7 General Features
Operates from a single external 12.800MHz local oscillator (TCXO or OCXO)
On-chip local oscillator watchdog circuit
Microprocessor interface can be 8-bit parallel (Intel or Motorola, multiplexed or nonmultiplexed) or SPI serial
Register set can be write-protected
11 of 149
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| PDF Descargar | [ Datasheet DS3101.PDF ] | |
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